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n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 1 of 160 revision 1.0 8 nano100 series datasheet arm ? cortex ? - m 32 - bit microcontroller numicro ? family nano100 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 2 of 160 revision 1.0 8 nano100 series datasheet table of contents list of figures ................................ ................................ ................................ ........................... 6 list of tables ................................ ................................ ................................ ............................. 7 1 general description ................................ ................................ ................................ ..... 8 2 features ................................ ................................ ................................ ........................... 10 2.1 nano100 features C base line ................................ ................................ ................. 10 2.2 nano110 features C lcd line ................................ ................................ .................. 16 2.3 nano120 features C usb connectivity line ................................ .............................. 22 2.4 nano130 features C advanced line ................................ ................................ .......... 28 3 parts information li st and pin configura tion ................................ ................ 34 3.1 numicro ? nano100 series selection code ................................ ................................ 34 3.2 numicro ? nano100 products selection guide ................................ ........................... 35 3.2.1 numicro ? nano100 base line selection guide ................................ .............................. 35 3.2.2 numicro ? nano110 lcd line selection guide ................................ ............................... 35 3.2.3 numicro ? nano120 usb connectivity line selection guide ................................ .......... 35 3.2.4 numicro ? nano130 advanced line selection guide ................................ ...................... 36 3.3 pin configuration ................................ ................................ ................................ ........ 37 3.3.1 numicro ? nano100 pin diagrams ................................ ................................ .................. 37 3.3.2 numicro ? nano110 pin diagrams ................................ ................................ .................. 40 3.3.3 numicro ? nano120 pin diagrams ................................ ................................ .................. 42 3.3.4 numicro ? nano130 pin diagrams ................................ ................................ .................. 45 3.4 pin description ................................ ................................ ................................ ........... 47 3.4.1 numicro ? nano100 pin description ................................ ................................ ................ 47 3.4.2 numicro ? nano110 pin description ................................ ................................ ................ 58 3.4.3 numicro ? nano120 pin description ................................ ................................ ................ 72 3.4.4 numicro ? nano130 pin description ................................ ................................ ................ 83 4 block diagram ................................ ................................ ................................ ................ 97 4.1 nano100 block diagram ................................ ................................ ............................ 97 4.2 nano110 block diagram ................................ ................................ ............................ 98 4. 3 nano120 block diagram ................................ ................................ ............................ 99 4.4 nano130 block diagram ................................ ................................ .......................... 100 5 functional descripti on ................................ ................................ ............................ 101 5.1 memory organization ................................ ................................ ............................... 101 5.1.1 overview ................................ ................................ ................................ ...................... 101 5.1.2 memory map ................................ ................................ ................................ ................ 101 5.2 nested vectored interrupt controller (nvic) ................................ ........................... 103 5.2.1 overview ................................ ................................ ................................ ...................... 103 5.2.2 featur es ................................ ................................ ................................ ....................... 103 5.3 system manager ................................ ................................ ................................ ...... 104 5.3.1 overview ................................ ................................ ................................ ...................... 104 5.3.2 featur es ................................ ................................ ................................ ....................... 104 5.4 clock controller ................................ ................................ ................................ ........ 105 5.4.1 overview ................................ ................................ ................................ ...................... 105
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 3 of 160 revision 1.0 8 nano100 series datasheet 5.4.2 features ................................ ................................ ................................ ....................... 105 5.5 analog to digital converter (adc) ................................ ................................ ........... 106 5.5.1 overview ................................ ................................ ................................ ...................... 106 5.5.2 features ................................ ................................ ................................ ....................... 106 5.6 digital to analog converter (dac) ................................ ................................ ........... 107 5.6.1 overview ................................ ................................ ................................ ...................... 107 5.6.2 features ................................ ................................ ................................ ....................... 107 5.7 dma controller ................................ ................................ ................................ ......... 108 5.7.1 overview ................................ ................................ ................................ ...................... 108 5.7.2 featur es ................................ ................................ ................................ ....................... 108 5.8 external bus interface ................................ ................................ .............................. 110 5.8.1 overview ................................ ................................ ................................ ...................... 110 5.8.2 features ................................ ................................ ................................ ....................... 110 5.9 flash memory controller (fmc) ................................ ................................ ............ 111 5.9.1 overview ................................ ................................ ................................ ...................... 111 5.9.2 features ................................ ................................ ................................ ....................... 111 5.10 general purpose i/o controller ................................ ................................ ................ 112 5.10.1 overview ................................ ................................ ................................ .................... 112 5.10.2 features ................................ ................................ ................................ ..................... 112 5.11 i 2 c ................................ ................................ ................................ ............................. 113 5.11.1 overview ................................ ................................ ................................ .................... 113 5.11.2 features ................................ ................................ ................................ ..................... 114 5.12 i 2 s ................................ ................................ ................................ ............................. 115 5.12.1 overview ................................ ................................ ................................ .................... 115 5.12.2 features ................................ ................................ ................................ ..................... 115 5.13 lcd display driver ................................ ................................ ................................ ... 116 5.13.1 overview ................................ ................................ ................................ .................... 116 5.13.2 featu res ................................ ................................ ................................ ..................... 116 5.14 pulse width modulation (pwm) ................................ ................................ ............... 117 5.14.1 overview ................................ ................................ ................................ .................... 117 5.14.2 featu res ................................ ................................ ................................ ..................... 118 5.15 rtc ................................ ................................ ................................ .......................... 11 9 5.15.1 overview ................................ ................................ ................................ .................... 119 5.15.2 features ................................ ................................ ................................ ..................... 119 5.16 smart card host interface (sc) ................................ ................................ ............... 119 5.16.1 overview ................................ ................................ ................................ .................... 119 5.16.2 features ................................ ................................ ................................ ..................... 119 5.17 spi ................................ ................................ ................................ ............................ 121 5.17.1 overview ................................ ................................ ................................ .................... 121 5.17.2 features ................................ ................................ ................................ ..................... 121 5.18 timer controller ................................ ................................ ................................ ........ 122 5.18.1 overview ................................ ................................ ................................ .................... 122 5.18.2 featu res ................................ ................................ ................................ ..................... 122 5.19 uart controller ................................ ................................ ................................ ....... 123
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 4 of 160 revision 1.0 8 nano100 series datasheet 5.19.1 overview ................................ ................................ ................................ .................... 123 5.19.2 the lin mode is selected by setting the lin_en bit in uart_fun_sel register. in lin mode, one start bit and 8 - bit data format with 1 - bit stop bit are required in accordance with the lin standard. features ................................ ................................ ................................ .............. 124 5.20 usb ................................ ................................ ................................ .......................... 126 5.20.1 overview ................................ ................................ ................................ .................... 126 5.20.2 features ................................ ................................ ................................ ..................... 126 5.21 watchdog timer controller ................................ ................................ ...................... 127 5.21.1 overview ................................ ................................ ................................ .................... 127 5.21.2 featu res ................................ ................................ ................................ ..................... 127 5.22 window watchdog timer controller ................................ ................................ ........ 128 5.22.1 overview ................................ ................................ ................................ .................... 128 5.22.2 featu res ................................ ................................ ................................ ..................... 128 6 arm ? cortex? - m0 core ................................ ................................ ............................. 129 6.1 overview ................................ ................................ ................................ ................... 129 6.2 features ................................ ................................ ................................ ................... 129 7 application circuit ................................ ................................ ................................ ..... 131 7.1 lcd charge pump ................................ ................................ ................................ ... 131 7.1.1 c - type 1/3 bias ................................ ................................ ................................ ............. 131 7.1.2 c - type 1/2 bias ................................ ................................ ................................ ............. 131 7.1.3 internal r - type ................................ ................................ ................................ .............. 131 7.1.4 external r - type ................................ ................................ ................................ ............. 132 7.2 adc application circuit ................................ ................................ ............................ 133 7.2.1 voltage reference source ................................ ................................ ........................... 133 7.3 dac application circuit ................................ ................................ ............................ 135 7.3.1 voltage reference source ................................ ................................ ........................... 135 7.4 whole chip application circuit ................................ ................................ ................. 137 8 power comsumption ................................ ................................ ................................ .. 138 9 electrical character istic ................................ ................................ ..................... 139 9.1 absolute maximum ratings ................................ ................................ ...................... 139 9.2 nano100/nano110/nano120/nano130 dc electrical characteristics ..................... 139 9.3 ac electrical characteristics ................................ ................................ .................... 145 9.3.1 external input clock ................................ ................................ ................................ ..... 145 9.3.2 external 4~24 mhz xtal oscillator ................................ ................................ ............. 145 9.3.3 external 32.768 khz crystal ................................ ................................ ......................... 146 9.3.4 internal 12 mhz oscillator ................................ ................................ ............................ 146 9.3.5 internal 10 khz oscillator ................................ ................................ ............................. 146 9.4 analog characteristics ................................ ................................ ............................. 146 9.4.1 12 - bit adc ................................ ................................ ................................ .................... 146 9.4.2 brown - out detector ................................ ................................ ................................ ....... 147 9.4.3 power - on reset ................................ ................................ ................................ ............ 148 9.4.4 temperature sensor ................................ ................................ ................................ ..... 148 9.4.5 12 - bit dac ................................ ................................ ................................ .................... 148 9.4.6 lc d ................................ ................................ ................................ .............................. 149 9.4.7 internal voltage reference ................................ ................................ ........................... 149
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 5 of 160 revision 1.0 8 nano100 series datasheet 9.4.8 usb phy specifications ................................ ................................ ............................... 149 9.5 flash dc electrical characteristics ................................ ................................ .......... 151 10 package dimensions ................................ ................................ ................................ ... 152 10.1 lqfp 128 (14x14x1.4 mm footprint 2.0 mm) ................................ ............................ 152 10.2 lqfp 64 ( 10 x1 0 x1.4 mm footprint 2.0 mm) ................................ .............................. 153 10.3 lqfp 64 (7x7x1.4 mm footprint 2.0 mm) ................................ ................................ .. 154 10.4 lqfp 48 (7x7x1.4 mm footprint 2.0 mm) ................................ ................................ .. 156 10.5 qfn48 (7x7x0.85 mm) ................................ ................................ ............................. 157 11 revision history ................................ ................................ ................................ .......... 158
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 6 of 160 revision 1.0 8 nano100 series datasheet list of figures figure 3 ? 1 numicro ? nano100 series selection code ................................ ................................ .. 34 figure 3 ? 2 numicro ? nano100 lqfp 128 - pin diagram ................................ ................................ 37 figure 3 ? 3 numicro ? nano100 lqfp 64 - pin diagram ................................ ................................ .. 38 figure 3 ? 4 numicro ? nano100 lqfp 48 - pin diagram ................................ ................................ ... 39 figure 3 ? 5 numicro ? nano110 lqfp 128 - pin diagram ................................ ................................ . 40 figure 3 ? 6 numicro ? nano110 lqfp 64 - pin diagram ................................ ................................ ... 41 figure 3 ? 7 numicro ? nano120 lqfp 128 - pin diagram ................................ ................................ . 42 figure 3 ? 8 numicro ? nano120 lqfp 64 - pin diagram ................................ ................................ ... 43 figure 3 ? 9 numicro ? nano120 lqfp 48 - pin diagram ................................ ................................ ... 44 figure 3 ? 10 numicro ? nano130 lqfp 128 - pin diagram ................................ ............................... 45 figure 3 ? 11 numicro ? nano130 lqfp 64 - pin diagram ................................ ................................ . 46 figure 4 ? 1 numicro ? nano100 block diagram ................................ ................................ .............. 97 figure 4 ? 2 numicro ? nano110 block diagram ................................ ................................ .............. 98 figure 4 ? 3 numicro ? nano120 block diagram ................................ ................................ .............. 99 figure 4 ? 4 numicro ? nano130 block diagram ................................ ................................ ............ 100 figure 6 ? 1 m0 functional block ................................ ................................ ................................ ... 129 figure 9 ? 1 typical crystal application circuit ................................ ................................ .............. 145
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 7 of 160 revision 1.0 8 nano100 series datasheet list of tables table 1 ? 1 connectivity support table ................................ ................................ ............................. 9 table 3 ? 1 nano100 base line selection table ................................ ................................ ............. 35 table 3 ? 2 nano110 lcd line selection table ................................ ................................ .............. 35 table 3 ? 3 nano120 usb connectivity line selection table ................................ ......................... 35 table 3 ? 4 nano130 advanced line selection table ................................ ................................ ..... 36 table 5 ? 12 uart baud rate equation ................................ ................................ ....................... 123 table 5 ? 13 uart baud rate setting ................................ ................................ .......................... 124
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 8 of 160 revision 1.0 8 nano100 series datasheet 1 general description the nano100 series ultra - low power 32 - bit microcontroller is embedded with arm ? cortex? - m0 core operated at a wide voltage range from 1.8v to 3.6v and runs up to 42 mhz frequency with 32k/64k/128k bytes embedded flash and 8k/16k - byte embedded sram. integra ting lcd 4x40 or 6x38 (com/segment), usb 2.0 full - speed function, rtc, 12 - bit sar adc, 12 - bit dac and provides high performance connectivity peripheral interfaces such as uart, spi, i 2 c, i 2 s, gpios, ebi (external bus interface) for external memory - mapped d evice access and iso - 7816 - 3 for smart card, the nano100 series supports brown - out detector, power - down mode with ram retention and fast wake - up via many peripheral interfaces. the nano100 series provides low power voltage, low power consumption, low stand by current, high integration peripherals, high - efficiency operation, fast wake - up function and the lowest cost 32 - bit microcontrollers. the nano100 series is suitable for a wide range of battery device applications such as: ? portable data collector ? portable medical monitor ? portable rfid reader ? portable barcode scanner ? security alarm system ? system supervisors ? power metering ? usb accessories ? smart card reader ? wireless game control device ? iptv remote smart keyboard ? wireless sensors node device (wsn) ? wire less rf4ce remote control ? wireless audio ? wireless automatic meter reader (amr) ? electronic toll collection (etc) the nano100 base line, an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core, operates at wide voltage range from 1.8 v to 3.6v and runs up to 42 mhz frequency with 32k/64k/128k bytes embedded flash and 8k/16k bytes embedded sram. it integrates rtc, 12 - channels 12 - bit sar adc, 2 - channels 12 - bit dac and provides high performance connectivity peripheral interfaces such as 2xuart, 3xspi, 2xi 2 c, i 2 s, gpios, ebi (external bus interface) for external memory - mapped device access and 3xiso - 7816 - 3 for smart card. the nano100 base line supports brown - out detector, power - down mode with ram retention and fast wake - up via many periphe ral interfaces. the nano110 lcd line, an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core, operates at wide voltage range from 1.8v to 3.6v and runs up to 42 mhz frequency with 32k/64k/128k bytes embedded flash and 8k/16k bytes embedded sram. it integrates lcd 4x40 or 6x38 (com/segment). rtc, 12 - channels 12 - bit sar adc, 2 - chann els 12 - bit dac and provides high performance connectivity peripheral interfaces such as 2xuart, 2xspi, 2xi 2 c, i 2 s, gpios, ebi (external bus interface) for external memory - mapped device access and 3xiso - 7816 - 3 for smart card. the nano110 lcd line supports b rown - out detector, power - down mode with ram retention and fast wake - up via many peripheral interfaces.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 9 of 160 revision 1.0 8 nano100 series datasheet the nano120 usb connectivity line, an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core, operates at wide voltage range from 1.8v to 3.6v and runs up to 42 mhz frequency with 32k/64k/128k bytes embedded flash and 8k/16k bytes embedded sram. it integrates usb 2.0 full - speed device function, rtc, 12 - channels12 - bit sar adc, 2 - channels 12 - bit dac and provides high performance conne ctivity peripheral interfaces such as 2xuart, 3xspi, 2xi2c, i2s, gpios, ebi (external bus interface) for external memory - mapped device access and 3xiso - 7816 - 3 for smart card. the nano120 usb connectivity line supports brown - out detector, power - down mode wi th ram retention and fast wake - up via many peripheral interfaces. the nano130 advanced line, an ultra - low power 32 - bit microcontroller with the embedded arm ? cortex? - m0 core, operates at wide voltage range from 1.8v to 3.6v and runs up to 42 mhz frequency with 32k/64k/128k bytes embedded flash and 8k/16k bytes embedded sram. it integrated lcd 4x40 or 6x38 (com/segment), usb 2.0 full - speed device function, rtc, 8 - channels 12 - bit sar adc, 2 - channels 12 - bit dac and provides high performance connectivity perip heral interfaces such as 2xuart, 2xspi, 2xi 2 c, i 2 s, gpios, ebi (external bus interface) for external memory - mapped device access and 3xiso - 7816 - 3 for smart card. the nano130 advanced line supports brown - out detector, power - down mode with ram retention and fast wake - up via many peripheral interfaces. product line uart spi i 2 c i 2 s usb lcd adc dac rtc ebi sc timer nano100 ? 1 connectivity support table
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 10 of 160 revision 1.0 8 nano100 series datasheet 2 features the equipped features are dependent on the product line and their sub products. 2.1 nano100 features C base line ? core ? arm ? cortex? - m0 core running up to 42 mhz ? one 24 - bit system timer ? supports low power sleep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? built - in 2.5v/2.0v/1.7v bod for wide o perating voltage range operation ? flash eprom memory ? runs up to 42 mhz with zero wait state for discontinuous address read access ? 64k/32k/123k bytes application program memory (aprom) ? 4 kb in system programming (isp) loader program memory (ldrom) ? programmab le data flash start address and memory size with 512 bytes page erase unit ? in system program (isp)/in application program (iap) to update on - chip flash eprom ? sram memory ? 16k/8k bytes embedded sram ? supports dma mode ? dma: supports 8 channels: one vdma chann el, 6 pdma channels and one crc channel ? vdma ? memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? pdma ? peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment transfer length in memory - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - wo rd/byte transfer data width from/to peripheral
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 11 of 160 revision 1.0 8 nano100 series datasheet ? supports address direction: increment, fixed, and wrap around ? crc ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? clock control ? flexible selection for different applications ? built - in 12 mhz osc, can be trimmed to 0.25% deviation within all temperature range when turning on auto - trim function (system must have external 32.768 khz crystal input) otherwise 12 mhz osc has 2 % deviation within all temperarure range. ? low power 10 khz osc for watchdog and low power system operation ? supports one pll, up to 120 mhz, for high perfor mance system operation and usb application (48 mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc function and low power system operation ? gpio ? three i/o modes: ? push - pull output ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin configured as interrupt source with edge/level setting ? supports high driver and high sink i/o mode ? supports input 5v tolerance, except pa.0 ~ pa.7, pd.0 ~ pd.1 and pc.6 ~ pc.7 ? timer ? supports 4 sets of 32 - bit timers, each with 24 - bit up - counting timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot,periodic, output toggle and continuous operation modes ? internal trigger event to adc, dac and pdm a ? supports pdma mode ? wake system up from power - down mode ? watchdog timer ? clock source from lirc (internal 10 khz low speed oscillator clock)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 12 of 160 revision 1.0 8 nano100 series datasheet ? selectable time - out period from 1.6 ms ~ 26 sec (depending on clock source) ? interrupt or reset selectable when watch dog time - out ? wake system up from power - down mode ? window watchdog timer(wwdt) ? 6 - bit down counter and 6 - bit compare value to make the window period flexible ? selectable wwdt clock pre - scale counter to make wwdt time - out interval variable. ? rtc ? supports softwa re compensation by setting frequency compensate register (fcr) ? supports rtc counter (second, minute, hour) and calendar counter (day, month, year) ? supports alarm registers (second, minute, hour, day, month, year) ? selectable 12 - hour or 24 - hour mode ? automatic leap year recognition ? supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? wake system up from power - down mode ? supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/capture ? supports 2 pwm modules, each has two 16 - bit pwm generators ? provides eight pwm outputs or four complementary paired pwm outputs ? each pwm generator equipped with one clock divider, one 8 - bit prescaler, two clock selectors, a nd one dead - zone generator for complementary paired pwm ? (shared with pwm timers) with eight 16 - bit digital capture timers provides eight rising/ falling/both capture inputs. ? supports one - shot and continuous mode ? supports capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? uart ports with flow control (tx, rx, ctsn and rtsn) ? supports irda (sir) function ? supports lin function ? supports rs - 485 9 bit mode and direction control. ? programmable baud rate generator ? supports pdma mode ? wake system up from p ower - down mode ? spi ? up to three sets of spi controller
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 13 of 160 revision 1.0 8 nano100 series datasheet ? master up to 32 mhz, and slave up to 16 mhz ? supports spi/microwire master/slave mode ? full duplex synchronous serial data transfer ? variable length of transfer data from 4 to 32 bits ? msb or lsb first data transfer ? rx and tx on both rising or falling edge of serial clock independently ? two slave/device select lines when spi controller is used as the master, and 1 slave/device select line when spi controller is used as the slave ? supports byte suspend mode in 32 - bit transmission ? supports two channel pdma requests, one for transmit and another for receive ? supports three wire mode, no slave select signal, bi - direction interface ? wake system up from power - down mode ? i 2 c ? up to two sets of i 2 c device ? master/slave up t o 1 mbit/s ? bi - directional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out count er overflows ? programmable clocks allowing for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition (four slave addresses with mask option) ? i 2 s ? interface with external audio codec ? operated as either master or slave mod e ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i 2 s and msb justified data format ? provides two 8 word fifo data buffers: one for transmitting and the other for receiving ? generates interrupt requests when b uffer levels cross a programmable boundary ? supports two pdma requests: one for transmitting and the other for receiving ? adc
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 14 of 160 revision 1.0 8 nano100 series datasheet ? 12 - bit sar adc up to 2msps conversion rate ? up to 12 - ch single - ended input from external pin (pa.0 ~ pa.7 and pd.0 ~ pd.3) ? six internal channels from dac0, dac1, internal reference voltage (int_vref), temperature sensor, avdd, and avss. ? supports three reference voltage sources from vref pin, internal reference voltage (int_vref), and avdd. ? supports single scan, single cycle scan, and continuous scan mode ? each channel with individual result register ? only scan on enabled channels ? threshold voltage detection (comparator function) ? conversion started by software programming or external input ? supports pdma mode ? supports up to four timer time - out events (t mr 0, tmr1, tmr 2 and tmr 3 ) to enable adc ? dac ? 12 - bit monotonic output with 400k conversion rate ? supports three reference voltage sources from vref pin, internal reference voltage (int_vref), and avdd. ? synchronized update capability for two dacs (group function) ? supports up to four timer time - out events (tmr0, tmr1, tmr 2 and tm r3 ), software or pdma to trigger dac to conversion ? smartcard (sc) ? compliant to iso - 7816 - 3 t=0, t=1 ? supports up to three iso - 7816 - 3 ports ? separates receive/transmit 4 b ytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? a 24 - bit and two 8 - bit time - out counters for answer to reset (atr) and waiting times processing ? supports auto inverse convention function ? supports stop clock level and clock stop (clock keep) function ? supports transmitter and receiver error retry and error limit function ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detect the card is removal ? supports uart mode (half duplex) ? ebi (external bus interface) support
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 15 of 160 revision 1.0 8 nano100 series datasheet ? accessible space: 64 kb in 8 - bit mod e or 128 kb in 16 - bit mode ? supports 8bit/16bit data width ? supports byte write in 16 - bit data width mode ? one built - in temperature sensor with 1 resolution ? 96 - bit unique id ? 128 - bit unique customer id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 128 - pin(14x14) / 64 - pin(7x7) / 48 - pin(7x7) / qfn 48 - pin(7x7)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 16 of 160 revision 1.0 8 nano100 series datasheet 2.2 nano110 features C lcd line ? core ? arm ? cortex? - m0 core running up to 42 mhz ? one 24 - bit system timer ? supports low power sleep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? built - in 2.5v/2.0v/1.7v bod for wide operating voltage range operation ? flash eprom memory ? runs up to 42 mhz with zero wait sta te for discontinuous address read access. ? 64k/32k/123k bytes application program memory (aprom) ? 4 kb in system programming (isp) loader program memory (ldrom) ? programmable data flash start address and memory size with 512 bytes page erase unit ? in system pr ogram (isp)/in application program (iap) to update on chip flash eprom ? sram memory ? 16k/8k bytes embedded sram ? supports dma mode ? dma : supports 8 channels: one vdma channel,6 pdma channels, and one crc channel ? vdma ? memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? pdma ? peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment tra nsfer length in memory - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - word/byte transfer data width from/to peripheral ? supports address direction: increment, fixed, and wrap around ? crc ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 17 of 160 revision 1.0 8 nano100 series datasheet crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? clock control ? flexible selection for different applications ? built - in 12 mhz osc, can be trimmed to 0.25% deviation within all temperature range when turning on auto - trim function (system must have external 32.768 khz crystal input) otherwise 12 m h z osc has 2 % deviation within all temperarure range. ? low power 10 khz osc for watchdog and low power system operation ? supports one pll, up to 120 mhz, for high performance system operation and usb application (48 mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc function and low power system operation ? gpio ? three i/o modes: ? push - pull output ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin configured as interrupt source with edge/level setting ? supports high driver and high sink i/o mode ? supports input 5v tolerance, except pa.0 ~ pa.7, pd.0 ~ pd.1 and pc.6 ~ pc.7) ? timer ? supports 4 sets of 32 - bit timers, each with 24 - bit up - timer and one 8 - bit pre - scale cou nter ? independent clock source for each timer ? provides one - shot,periodic, output toggle and continuous operation modes ? internal trigger event to adc, dac and pdma module ? supports pdma mode ? wake system up from power - down mode ? watchdog timer ? clock source from lirc (internal 10 khz low speed oscillator clock) ? selectable time - out period from 1.6 ms ~ 26 sec (depending on clock source) ? interrupt or reset selectable when watchdog time - out
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 18 of 160 revision 1.0 8 nano100 series datasheet ? wake system up from power - down mode ? window watchdog timer(wwdt) ? 6 - bit do wn counter and 6 - bit compare value to make the window period flexible ? selectable wwdt clock pre - scale counter to make wwdt time - out interval variable. ? rtc ? supports software compensation by setting frequency compensate register (fcr) ? supports rtc counter ( second, minute, hour) and calendar counter (day, month, year) ? supports alarm registers (second, minute, hour, day, month, year) ? selectable 12 - hour or 24 - hour mode ? automatic leap year recognition ? supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? wake system up from power - down mode ? supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/capture ? supports 2 pwm modules, each has two 16 - bit pwm generators ? provides eight pwm outputs or four complementary paired pwm outputs ? each pwm generator equipped with one clock divider, one 8 - bit prescaler, two clock selectors, and one dead - zone generator for complementary paired pwm ? (shared with pwm timers) with eight 16 - bit digital capture timers provides eight rising/ falling/both capture inputs. ? supports capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? uart ports with flow control (tx, rx, ctsn and rtsn) ? supports irda (sir) function ? supports lin functi on ? supports rs - 485 9 bit mode and direction control (low density only) ? programmable baud rate generator ? supports pdma mode ? wake system up from power - down mode ? spi ? up to three sets of spi controller ? master up to 32 mhz, and slave up to 16 mhz ? supports spi/m icrowire master/slave mode ? full duplex synchronous serial data transfer
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 19 of 160 revision 1.0 8 nano100 series datasheet ? variable length of transfer data from 4 to 32 bits ? msb or lsb first data transfer ? rx and tx on both rising or falling edge of serial clock independently ? two slave/device select lines when spi controller is as the master, and 1 slave/device select line when spi controller is as the slave ? supports byte suspend mode in 32 - bit transmission ? supports two channel pdma requests, one for transmit and another for receive ? supports three wire mode , no slave select signal, bi - direction interface ? wake system up from power - down mode ? i 2 c ? up to two sets of i 2 c device ? master/slave up to 1mbit/s ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allowing devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? programmable clocks allow versatile rate control ? supports 7 - bit addressing mode ? supports multiple address reco gnition (four slave address with mask option) ? i 2 s ? interface with external audio codec ? operated as either master or slave mode ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i 2 s and msb justified data format ? provides two 8 word fifo data buffers: one for transmitting and the other for receiving ? generates interrupt requests when buffer levels cross a programmable boundary ? supports two pdma requests: one for transmitting and the other for receiving ? adc ? 12 - bit sar adc up to 2msps conversion rate ? up to 12 - ch single - ended input from external pin (pa.0 ~ pa.7 and pd.0 ~ pd.3) ? six internal channels from dac0, dac1, internal reference voltage (int_vref),
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 20 of 160 revision 1.0 8 nano100 series datasheet temperature sensor, avdd, and avss ? supports three reference vol tage sources from vref pin, internal reference voltage (int_vref), and avdd. ? single scan/single cycle scan/continuous scan ? each channel with individual result register ? only scan on enabled channels ? threshold voltage detection (comparator function) ? conversi on start by software programming or external input ? supports pdma mode ? supports up to four timer time - out events (tmr0, tmr1, tmr 2 , and t mr 3 ) to enable adc ? dac ? 12 - bit monotonic output with 400k conversion rate ? supports three reference voltage sources from v ref pin, internal reference voltage (int_vref), and avdd. ? synchronized update capability for two dacs (group function) ? supports up to four timer time - out events (tmr0, tmr1, tmr 2 and tmr 3 ), software or pdma to trigger dac to conversion ? smartcard (sc) ? compl iant to iso - 7816 - 3 t=0, t=1 ? supports up to three iso - 7816 - 3 ports ? separates receive / transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? a 24 - bit and two 8 - bit time - out counter for answer to reset (atr) and waiting times processing ? supports auto inverse convention function ? supports stop clock level and clock stop (clock keep) function ? supports transmitter and receiver error retry and error limit function ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detect the card is removal ? supports uart mode (half duplex) ? lcd ? lcd driver for up to 4 com x 40 seg or 6 com x 38 seg ? supports static,1/2 bias and 1/3 bias voltage ? four display modes; static, 1/2 duty, 1/3 duty,1/4 duty, 1/5 duty and 1/6 duty.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 21 of 160 revision 1.0 8 nano100 series datasheet ? selectable lcd frequency by frequency divider ? c onfigurable frame frequency ? internal charge pump, adjustable contrast adjustment ? configurable charge pump frequency ? blinking capability ? supports r - type/c - type method ? lcd frame interrupt ? one built - in temperature sensor with 1 resolution ? 96 - bit unique id ? 12 8 - bit unique customer id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 128 - pin(14x14) / 64 - pin ( 10 x 10 ) / 64 - pin(7x7)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 22 of 160 revision 1.0 8 nano100 series datasheet 2.3 nano120 features C usb connectivity line ? core ? arm ? cortex? - m0 core running up to 42 mhz ? one 24 - bit system timer ? supports low power sleep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? built - in 2.5v/2.0v/1.7v bod for wide operating volt age range operation ? flash eprom memory ? runs up to 42 mhz with zero wait state for discontinuous address read access. ? 64k/32k/123k bytes application program memory (aprom) ? 4kb in system programming (isp) loader program memory (ldrom) ? programmable data flash start address and memory size with 512 bytes page erase unit ? in system program (isp)/in application program (iap) to update on chip flash eprom ? sram memory ? 16k/8k bytes embedded sram ? supports pdma mode ? dma: support 8 channels: one vdma channel, 6 pdma ch annels, and one crc channel ? vdma ? memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? pdma ? peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment transfer length in memory - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - word/b yte transfer data width from/to peripheral ? supports address: increment, fixed, and wrap around ? crc ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 23 of 160 revision 1.0 8 nano100 series datasheet crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? clock control ? flexible selection for different applications ? built - in 12mhz osc, can be trimmed to 0.25% deviation within all temperature range when turning on auto - trim functio n (system must have external 32.768 khz crystal input) otherwise 12 m hz osc has 2 % deviation within all temperarure rang e ? low power 10 khz osc for watchdog and low power system operatin ? supports one pll, up to 120 mhz, for high performance system operation and usb application (48 mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc function and low power system operation ? gpio ? three i/o modes: ? push - pull output ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin can be configured as interrupt source with edge/level setting ? high driver and high sink io mode support ? supports input 5v tolerance (except adc and dac shared pins) ? timer ? supports 4 sets of 32 - bit tim ers, each with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot,periodic, output toggle and continuous operation modes ? internal trigger event to adc, dac and pdma module ? supports pdma mode ? wake syste m up from power - down mode ? watchdog timer ? clock source from lirc. (internal 10 khz low speed oscillator clock) ? selectable time - out period from 1.6 ms ~ 26 sec (depending on clock source) ? interrupt or reset selectable on watchdog time - out ? wake system up from power - down mode
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 24 of 160 revision 1.0 8 nano100 series datasheet ? window watchdog timer(wwdt) ? 6 - bit down counter and 6 - bit compare value to make the window period flexible ? selectable wwdt clock pre - scale counter to make wwdt time - out interval variable. ? rtc ? supports software compensation by setting frequency compensate register (fcr) ? supports rtc counter (second, minute, hour) and calendar counter (day, month, year) ? supports alarm registers (second, minute, hour, day, month, year) ? selectable 12 - hour or 24 - hour mode ? automatic leap year recognition ? sup ports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? wake system up from power - down or idle mode ? support 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/ca pture ? supports 2 pwm module, each has two 16 - bit pwm generators ? provide eight pwm outputs or four complementary paired pwm outputs ? each pwm generator equipped with one clock divider, one 8 - bit prescaler, two clock selectors, and one dead - zone generator for complementary paired pwm ? (shared with pwm timers) with eight 16 - bit digital capture timers provides eight rising/ falling/both capture inputs. ? supports one shot and continuous mode ? supports capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? u art ports with flow control (tx, rx, ctsn and rtsn) ? supports irda (sir) function ? supports lin function ? supports rs - 485 9 bit mode and direction control. (low density only) ? programmable baud rate generator ? supports pdma mode ? wake system up from power - down m ode ? spi ? up to three sets of spi controller ? master up to 32 mhz, and slave up to 16 mhz ? supports spi/microwire master/slave mode ? full duplex synchronous serial data transfer
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 25 of 160 revision 1.0 8 nano100 series datasheet ? variable length of transfer data from 4 to 32 bits ? msb or lsb first data transfer ? rx and tx on both rising or falling edge of serial clock independently ? two slave/device select lines when spi controller is as the master, and 1 slave/device select line when spi controller is as the slave ? supports byte suspend mode in 32 - bit transmission ? supports two channel pdma requests, one for transmit and another for receive ? supports three wire, no slave select signal, bi - direction interface ? wake system up from power - down mode ? i 2 c ? up to two sets of i 2 c device ? master/slave up to 1mbit/s ? bi - directional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allowing devices with different bit rates to com municate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? programmable clocks allow versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition (four slave addresses with mask option) ? i 2 s ? interface with external audio codec ? operated as either master or slave mode ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i 2 s and msb justified data format ? provides two 8 word fifo data buffers: one for transmitting and the other for receiving ? generates interrupt requests when buffer levels cross a programmabl e boundary ? supports two pdma requests: one for transmitting and the other for receiving ? adc ? 12 - bit sar adc up to 2msps conversion rate ? up to 12 - ch single - ended input from external pin (pa.0 ~ pa.7 and pd.0 ~ pd.3).
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 26 of 160 revision 1.0 8 nano100 series datasheet ? six internal channels from dac0, dac1, in ternal reference voltage (int_vref), temperature sensor, avdd, and avss. ? supports three reference voltage sources from vref pin, internal reference voltage (int_vref), and avdd ? supports single scan, single cycle scan, and continuous scan modes ? each channel with individual result register ? only scan on enabled channels ? threshold voltage detection (comparator function) ? conversion start by software programming or external input ? supports pdma mode ? supports up to four timer time - out events (tmr0, tmr1, tmr 2 and tmr 3 ) to enable adc ? dac ? 12 - bit monotonic output with 400k conversion rate ? supports three reference voltage sources from vref pin, internal reference voltage (int_vref), and avdd. ? synchronized update capability for two dacs (group function) ? supports up to f our timer time - out event (tmr0 , tmr1, tmr 2 and tmr 3 ), software or pdma to trigger dac to conversion ? smartcard (sc) ? compliant to iso - 7816 - 3 t=0, t=1 ? supports up to three iso - 7816 - 3 ports ? separates receive / transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? a 24 - bit and two 8 - bit time - out counter for answer to reset (atr) and waiting times processing ? supports auto inverse c onvention function ? supports stop clock level and clock stop (clock keep) function ? supports transmitter and receiver error retry and error limit function ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports ha rdware deactivation sequence process ? supports hardware auto deactivation sequence when detect the card is removal ? supports uart mode (half duplex) ? usb 2.0 full - speed device ? one set of usb 2.0 fs device 12 m bps ? on - chip usb transceiver
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 27 of 160 revision 1.0 8 nano100 series datasheet ? provides 1 interrupt source with 4 interrupt events ? supports control, bulk in/out, interrupt and isochronous transfers ? auto suspend function when no bus signaling for 3 ms ? provides 8 programmable endpoints ? includes 512 bytes internal sram as usb buffer ? provides remote wake - up capability ? ebi (external bus interface) support ? accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode ? supports 8bit/16bit data width ? supports byte write in 16 - bit data width mode ? one built - in temperature sensor with 1 resolution ? 96 - bit unique id ? 128 - bit unique customer id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 128 - pin(14x14) / 64 - pin(7x7) / 48 - pin(7x7)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 28 of 160 revision 1.0 8 nano100 series datasheet 2.4 nano130 features C advanced line ? core ? arm ? cortex? - m0 core running up to 42 mhz ? one 24 - bit system timer ? supports low power sleep mode ? single - cycle 32 - bit hardware multiplier ? nvic for the 32 interrupt inputs, each with 4 - levels of priority ? serial wire debug supports with 2 watchpoints/4 breakpoints ? brown - out ? built - in 2.5v/2.0v/1.7v bod for wide operating voltage range operation ? flash eprom memory ? runs up to 42 mhz with zero wait state for discontinuous address read access. ? 64k/32k/123k bytes application program memory (aprom) ? 4kb in system programming (isp) loader program memory (ldrom) ? programmable data flash start ad dress and memory size with 512 bytes page erase unit ? in system program (isp)/in application program (iap) to update on chip flash eprom ? sram memory ? 16k/8k bytes embedded sram ? supports dma mode ? dma : supports 8 channels: one vdma channel,6 pdma channels, and one crc egiste ? vdma ? memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? pdma ? periph eral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment transfer length in memory - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - word/byte transfer data width from/to peripheral ? supports address direction: increment, fixed, and wrap around ? crc ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 29 of 160 revision 1.0 8 nano100 series datasheet crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8 : x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? clock control ? flexible selection for different applications ? built - in 12mhz osc, can be trimmed to 0.25% deviation within all temperature range when turning on auto - trim function (system must have external 32.768 khz crystal input) otherwise 12 m hz osc has 2 % deviation within all temperarure rang e. ? low power 10 khz osc for watchdog and low power system operation ? supports one pll, up to 120 mhz, for high performance system operation and usb application (48 mhz). ? external 4~24 mhz crystal input for precise timing operation ? external 32.768 khz crystal input for rtc fun ction and low power system operation ? gpio ? three i/o modes: ? push - pull output ? open - drain output ? input only with high impendence ? all inputs with schmitt trigger ? i/o pin configured as interrupt source with edge/level setting ? supports high driver and high sink i/o mode ? supports input 5v tolerance (except adc and dac shared pins) ? timer ? supports 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit pre - scale counter ? independent clock source for each timer ? provides one - shot,periodic, output toggle and continuo us operation modes ? supports internal trigger event to adc, dac and pdma module ? wake system up from power - down mode ? watchdog timer ? clock source is from lirc. (internal 10 khz low speed oscillator clock) ? selectable time - out period from 1.6ms ~ 26sec (depend s on clock source) ? interrupt or reset selectable on watchdog time - out ? wdt can wake system up from power - down mode ? window watchdog timer(wwdt)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 30 of 160 revision 1.0 8 nano100 series datasheet ? 6 - bit down counter and 6 - bit compare value to make the window period flexible ? selectable wwdt clock pre - scale counter to make wwdt time - out interval variable. ? rtc ? supports software compensation by setting frequency compensate register (fcr) ? supports rtc counter (second, minute, hour) and calendar counter (day, month, year) ? supports alarm registers (second, minute , hour, day, month, year) ? selectable 12 - hour or 24 - hour mode ? automatic leap year recognition ? supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? wake system up from power - down or idle mode ? supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers ? pwm/capture ? supports 2 pwm module, each with two 16 - bit pwm generators ? provides eight pwm outputs or four complementary paired pwm outputs ? each pwm generator eq uipped with one clock divider, one 8 - bit prescaler, two clock selectors, and one dead - zone generator for complementary paired pwm ? (shared with pwm timers) with eight 16 - bit digital capture timers provides eight rising/ falling/both capture inputs. ? supports capture interrupt ? uart ? up to two 16 - byte fifo uart controllers ? uart ports with flow control (tx, rx, ctsn and rtsn) ? supports irda (sir) function ? supports lin function ? supports rs - 485 9 bit mode and direction control (low density only) ? programmable baud rate generator ? supports pdma mode ? wake system up from power - down or idle mode ? spi ? up to 3 sets of spi controller ? master up to 32 mhz, and slave up to 16 mhz ? supports spi/microwire master/slave mode ? full duplex synchronous serial data transfer ? variable leng th of transfer data from 4 to 32 bits ? msb or lsb first data transfer
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 31 of 160 revision 1.0 8 nano100 series datasheet ? rx and tx on both rising or falling edge of serial clock independently ? two slave/device select lines when used as the master, and 1 slave/device select line when used as the slave ? support s byte suspend mode in 32 - bit transmission ? supports two channel pdma request, one for transmit and another for receive ? supports three wire, no slave select signal, bi - direction interface ? wake system up from power - down or idle mode ? i 2 c ? up to two sets of i 2 c device ? master/slave up to 1mbit/s ? bi - directional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronizatio n allowing devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? built - in 14 - bit time - out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows ? programmable clocks allowing for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition (four slave addresses with mask option) ? i 2 s ? interface with external audio codec ? operate as either master or slave mode ? capable of handling 8, 16, 24 and 32 bit word sizes ? supports mono and stereo audio data ? supports i 2 s and msb justified data format ? provides two 8 word fifo data buffers: one for transmitting and the other for receivin g ? generates interrupt requests when buffer levels cross a programmable boundary ? supports two pdma requests: one for transmitting and the other for receiving ? adc ? 12 - bit sar adc up to 2msps conversion rate ? up to 12 - ch single - ended input from external pin (pa .0 ~ pa.7 and pd.0 ~ pd.3) ? six internal channels from dac0, dac1, internal reference voltage (int_vref), temperature sensor, avdd, and avss. ? supports three reference voltage sources from vref pin, internal reference
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 32 of 160 revision 1.0 8 nano100 series datasheet voltage (int_vref), and avdd ? single scan /single cycle scan/continuous scan ? each channel with individual result register ? scan on enabled channels ? threshold voltage detection (comparator function) ? conversion start by software programming or external input ? supports pdma mode ? supports up to four tim er time - out events (tmr0, tmr1, tmr 2 and tmr 3 ) to enable adc ? dac ? 12 - bit monotonic output with 400k conversion rate ? supports three reference voltage sources from vref pin, internal reference voltage (int_vref), and avdd. ? synchronized update capability for two dacs (group function) ? supports up to four timer time - out events (tmr0, tmr1, tmr 2 and tmr 3 ), software or pdma to trigger dac to conversion ? smartcard (sc) ? compliant to iso - 7816 - 3 t=0, t=1 ? supports up to three iso - 7816 - 3 ports ? separates receive/transmit 4 bytes entry fifo for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? a 24 - bit and two 8 - bit time - out counter for answer to reset (atr) and waiting tim es processing ? supports auto inverse convention function ? supports stop clock level and clock stop (clock keep) function ? supports transmitter and receiver error retry and error limit function ? supports hardware activation sequence process ? supports hardware wa rm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detecting the card is removed ? support uart mode (half duplex) ? lcd ? lcd driver for up to 4 com x 40 seg or 6 com x 38 seg ? supports st atic,1/2 bias and 1/3 bias voltage ? four display modes: static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty. ? selectable lcd frequency by frequency divider
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 33 of 160 revision 1.0 8 nano100 series datasheet ? configurable frame frequency ? internal charge pump, adjustable contrast adjustment ? configurable charge pump frequency ? blinking capability ? supports r - type/c - type method ? lcd frame interrupt ? usb 2.0 full - speed device ? one set of usb 2.0 fs device 12 m bps ? on - chip usb transceiver ? provides 1 interrupt source with 4 interrupt events ? supports control, bulk i n/out, interrupt and isochronous transfers ? auto suspend function when no bus signaling for 3 ms ? provides 8 programmable endpoints ? includes 512 bytes internal sram as usb buffer ? provides remote wake - up capability ? ebi (external bus interface) ? accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode ? supports 8bit/16bit data width ? supports byte write in 16 - bit data width mode ? one built - in temperature sensor with 1 resolution ? 96 - bit unique id ? 128 - bit unique customer id ? operating temperature: - 40 ~85 ? packages: ? all green package (rohs) ? lqfp 128 - pin(14x14) / 64 - pin (7x7)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 34 of 160 revision 1.0 8 nano100 series datasheet 3 parts information li st and pin configura tion 3.1 numicro ? nano100 series selection code figure 3 ? 1 numicro ? nano100 series selection code n a n o 1 x - x x u l t r a - l o w p o w e r m c u 0 : b a s e l i n e 1 : l c d l i n e 2 : u s b c o n n e c t i v i t y l i n e 3 : l c d + u s b c o n n e c t i v i t y l i n e c p u c o r e 1 : c o r t e x - m 0 5 / 7 : a r m 7 9 : a r m 9 t e m p e r a t u r e n : - 4 0 v e r s i o n b n p r o d u c t l i n e f u n c t i o n x p a c k a g e t y p e n : q f n 4 8 ( 7 x 7 m m ) l : l q f p 4 8 ( 7 x 7 m m ) r : l q f p 6 4 ( 1 0 x 1 0 m m ) s : l q f p 6 4 ( 7 x 7 m m ) k : l q f p 1 2 8 ( 1 4 x 1 4 m m ) x s r a m s i z e 0 : 1 : 2 : 3 : f l a s h r o m a : b : c : d : e : r e s e r v e d 0 ~ 9 s u b p r o d u c t l i n e a : v e r s i o n b : v e r s i o n 8 k b 1 6 k b 3 2 k b 6 4 k b 1 2 8 k b 2 k b 4 k b 8 k b 1 6 k b
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 35 of 160 revision 1.0 8 nano100 series datasheet 3.2 numicro ? nano100 products selection guide 3.2.1 numicro ? nano100 base line selection guide *marked in the table (2+3) means 2 uart+ 3 iso - 7816 uart. lqfp64*:7x7mm *iso - 7816 uart supports half duplex mode. table 3 ? 1 nano100 base line selection table 3.2.2 numicro ? nano110 lcd line selection guide *marked in the table (2+3) means 2 uart+ 3 iso - 7816 uart. lqfp64*:7x7mm *iso - 7816 uart supports half duplex mode. table 3 ? 2 nano110 lcd line selection table 3.2.3 numicro ? nano120 usb connectivity line selection guide *marked in the table (2+3) means 2 uart+ 3 iso - 7816 uart. lqfp64*:7x7mm *iso - 7816 uart supports half duplex mode. table 3 ? 3 nano120 usb connectivity line selection table uart* spi i 2 c usb NANO100NC2BN 32 8 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 qfn48 -40 to +85 nano100nd2bn 64 8 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 qfn48 -40 to +85 nano100nd3bn 64 16 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 qfn48 -40 to +85 nano100ne3bn 128 16 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 qfn48 -40 to +85 nano100lc2bn 32 8 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 lqfp48 -40 to +85 nano100ld2bn 64 8 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 lqfp48 -40 to +85 nano100ld3bn 64 16 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 lqfp48 -40 to +85 nano100le3bn 128 16 configurable 4 38 4 2+2 3 2 - 1 6 7 - 8 - 2 2 lqfp48 -40 to +85 nano100sc2bn 32 8 configurable 4 52 4 2+3 3 2 - 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano100sd2bn 64 8 configurable 4 52 4 2+3 3 2 - 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano100sd3bn 64 16 configurable 4 52 4 2+3 3 2 - 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano100se3bn 128 16 configurable 4 52 4 2+3 3 2 - 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano100kd3bn 64 16 configurable 4 86 4 2+3 3 2 - 1 8 12 8 - 2 3 lqfp128 -40 to +85 nano100ke3bn 128 16 configurable 4 86 4 2+3 3 2 - 1 8 12 8 - 2 3 lqfp128 -40 to +85 part no. flash (kbytes) sram (kbytes) data flash (kbytes) operating temp. range (c ) icp isp iap package i 2 s pwm (16-bit) lcd isp rom (kbytes) i/o timer (32-bit) connectivity adc (12-bit) rtc pdma ebi dac (12-bit) iso-7816-3* irc 10khz 12mhz uart* spi i 2 c usb nano110sc2bn 32 8 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano110sd2bn 64 8 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano110sd3bn 64 16 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano110se3bn 128 16 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano110rc2bn 32 8 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64 -40 to +85 nano110rd2bn 64 8 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64 -40 to +85 nano110rd3bn 64 16 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64 -40 to +85 nano110re3bn 128 16 configurable 4 51 4 2+3 3 2 - 1 7 7 - 8 4x31, 6x29 2 3 lqfp64 -40 to +85 nano110kc2bn 32 8 configurable 4 86 4 2+3 3 2 - 1 8 12 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano110kd2bn 64 8 configurable 4 86 4 2+3 3 2 - 1 8 12 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano110kd3bn 64 16 configurable 4 86 4 2+3 3 2 - 1 8 12 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano110ke3bn 128 16 configurable 4 86 4 2+3 3 2 - 1 8 12 8 4x40, 6x38 2 3 lqfp128 -40 to +85 part no. flash (kbytes) sram (kbytes) data flash (kbytes) isp rom (kbytes) i/o package operating temp. range (c ) icp isp iap dac (12-bit) iso-7816-3* irc 10khz 12mhz pdma lcd timer (32-bit) rtc ebi connectivity i 2 s pwm (16-bit) adc (12-bit) uart* spi i 2 c usb nano120lc2bn 32 8 configurable 4 34 4 2+2 3 2 1 1 4 7 - 8 - 2 2 lqfp48 -40 to +85 nano120ld2bn 64 8 configurable 4 34 4 2+2 3 2 1 1 4 7 - 8 - 2 2 lqfp48 -40 to +85 nano120ld3bn 64 16 configurable 4 34 4 2+2 3 2 1 1 4 7 - 8 - 2 2 lqfp48 -40 to +85 nano120le3bn 128 16 configurable 4 34 4 2+2 3 2 1 1 4 7 - 8 - 2 2 lqfp48 -40 to +85 nano120sc2bn 32 8 configurable 4 48 4 2+3 3 2 1 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano120sd2bn 64 8 configurable 4 48 4 2+3 3 2 1 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano120sd3bn 64 16 configurable 4 48 4 2+3 3 2 1 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano120se3bn 128 16 configurable 4 48 4 2+3 3 2 1 1 8 7 - 8 - 2 3 lqfp64* -40 to +85 nano120kd3bn 64 16 configurable 4 86 4 2+3 3 2 1 1 8 8 8 - 2 3 lqfp128 -40 to +85 nano120ke3bn 128 16 configurable 4 86 4 2+3 3 2 1 1 8 8 8 - 2 3 lqfp128 -40 to +85 part no. flash (kbytes) sram (kbytes) data flash (kbytes) isp rom (kbytes) timer (32-bit) connectivity i 2 s pwm (16-bit) adc (12-bit) i/o rtc ebi dac (12-bit) iso-7816-3* pdma lcd icp isp iap package operating temp. range (c ) irc 10khz 12mhz
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 36 of 160 revision 1.0 8 nano100 series datasheet 3.2.4 numicro ? nano130 advanced line selection guide *marked in the table (2+3) means 2 uart+ 3 iso - 7816 uart. lqfp64*:7x7mm *iso - 7816 uart supports half duplex mode. table 3 ? 4 nano130 advanced line selection table uart* spi i 2 c usb nano130sc2bn 32 8 configurable 4 47 4 2+3 3 2 1 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano130sd2bn 64 8 configurable 4 47 4 2+3 3 2 1 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano130sd3bn 64 16 configurable 4 47 4 2+3 3 2 1 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano130se3bn 128 16 configurable 4 47 4 2+3 3 2 1 1 7 7 - 8 4x31, 6x29 2 3 lqfp64* -40 to +85 nano130kc2bn 32 8 configurable 4 86 4 2+3 3 2 1 1 8 8 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano130kd2bn 64 8 configurable 4 86 4 2+3 3 2 1 1 8 8 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano130kd3bn 64 16 configurable 4 86 4 2+3 3 2 1 1 8 8 8 4x40, 6x38 2 3 lqfp128 -40 to +85 nano130ke3bn 128 16 configurable 4 86 4 2+3 3 2 1 1 8 8 8 4x40, 6x38 2 3 lqfp128 -40 to +85 i/o ebi timer (32-bit) connectivity i 2 s pwm (16-bit) adc (12-bit) rtc part no. flash (kbytes) sram (kbytes) data flash (kbytes) isp rom (kbytes) pdma lcd dac (12-bit) iso-7816-3* package operating temp. range (c ) icp isp iap irc 10khz 12mhz
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 37 of 160 revision 1.0 8 nano100 series datasheet 3.3 pin configuration 3.3.1 numicro ? nano100 pin diagrams 3.3.1.1 numicro ? nano100 lqfp 128 - pin figure 3 ? 2 numicro ? nano100 lqfp 128 - pin diagram n c p d . 4 p d . 5 p b . 1 2 x 3 2 o n c x 3 2 i p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 n c l d o _ c a p n c n c n r e s e t v s s v s s n c v d d n c p f . 4 p e . 1 4 p a . 7 / a d 7 p a . 6 / a d 6 p a . 5 / a d 5 p a . 4 / a d 4 p a . 3 / a d 3 p a . 2 / a d 2 a v s s a v s s v s s v s s n c v d d n c i c e _ c l k / p f . 1 p c . 6 p f . 5 v s s p e . 1 5 p c . 5 p d . 1 5 p d . 1 4 p d . 7 p b . 2 p b . 1 p b . 0 n c n c n c n c n c p e . 7 p e . 8 p e . 9 p e . 1 0 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 i c e _ d a t / p f . 0 p a . 1 2 n a n o 1 0 0 l q f p 1 2 8 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 3 p b . 1 4 p b . 1 3 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p d . 1 2 p d . 1 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 p e . 1 1 p e . 1 2 p d . 6 p b . 3 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p a . 1 / a d 1 p a . 0 / a d 0 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 p v s s p b . 8 p c . 1 5 p c . 1 4 p b . 1 5 n c x t 1 _ i n x t 1 _ o u t p c . 7 n c v d d n c v s s v s s v s s v s s 3 2 3 1 3 0 2 9 2 8 2 7 2 6 n c p e . 6 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 9 p b . 1 0 p b . 1 1 p e . 5 n c 6 5 6 6 6 7 6 8 6 9 7 0 7 1 p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 v r e f n c a d 8 / p d . 0 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 a d 9 / p d . 1 a d 1 0 / p d . 2 a d 1 1 / p d . 3 a v d d 9 7 n c
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 38 of 160 revision 1.0 8 nano100 series datasheet 3.3.1.2 numicro ? nano100 lqfp 64 - pin figure 3 ? 3 numicro ? nano100 lqfp 64 - pin diagram a d 5 / p a . 5 a d 6 / p a . 6 v r e f p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o _ c a p v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t p b . 8 p a . 4 / a d 4 p a . 3 / a d 3 p a . 2 / a d 2 p a . 1 / a d 1 p a . 0 / a d 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 p c . 1 1 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p d . 1 5 p d . 1 4 p d . 7 p d . 6 p b . 3 p b . 2 p b . 1 p b . 0 n a n o 1 0 0 l q f p 6 4 - p i n
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 39 of 160 revision 1.0 8 nano100 series datasheet 3.3.1.3 numicro ? nano100 lqfp /qfn 48 - pin figure 3 ? 4 numicro ? nano100 lqfp 48 - pin diagram a d 5 / p a . 5 a d 6 / p a . 6 v r e f p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 l d o _ c a p v d d v s s p c . 7 p c . 6 p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t p b . 8 p a . 4 / a d 4 p a . 3 / a d 3 p a . 2 / a d 2 p a . 1 / a d 1 p a . 0 / a d 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 a v d d p v s s p b . 9 p b . 1 0 p b . 1 1 p e . 5 p b . 3 p b . 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n a n o 1 0 0 l q f p / q f n 4 8 - p i n p b . 1 p b . 0 p c . 0 p c . 1 p c . 2 p c . 3
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 40 of 160 revision 1.0 8 nano100 series datasheet 3.3.2 numicro ? nano110 pin diagrams 3.3.2.1 numicro ? nano110 lqfp 128 - pin figure 3 ? 5 numicro ? nano110 lqfp 128 - pin diagram n c l c d _ s e g 3 5 / p d . 4 l c d _ s e g 3 4 / p d . 5 l c d _ s e g 2 4 / p b . 1 2 x 3 2 o n c x 3 2 i l c d _ s e g 2 3 / p a . 1 1 l c d _ s e g 2 2 / p a . 1 0 l c d _ s e g 2 1 / p a . 9 l c d _ s e g 2 0 / p a . 8 l c d _ s e g 1 3 / p b . 4 l c d _ s e g 1 2 / p b . 5 l c d _ s e g 1 1 / p b . 6 l c d _ s e g 1 0 / p b . 7 n c l d o _ c a p n c n c n r e s e t v s s v s s n c v d d n c p f . 4 l c d _ s e g 2 8 / p e . 1 4 p a . 7 / a d 7 / l c d _ s e g 3 6 p a . 6 / a d 6 / l c d _ s e g 3 7 p a . 5 / a d 5 / l c d _ s e g 3 8 p a . 4 / a d 4 / l c d _ s e g 3 9 p a . 3 p a . 2 a v s s a v s s v s s v s s n c v d d n c i c e _ c k / p f . 1 p c . 6 p f . 5 v s s l c d _ s e g 2 9 / p e . 1 5 p c . 5 / l c d _ c o m 3 p d . 1 5 / l c d _ s e g 0 ( c o m 4 ) p d . 1 4 / l c d _ s e g 1 ( c o m 5 ) p d . 7 / l c d _ s e g 2 p b . 2 / l c d _ s e g 5 p b . 1 / l c d _ s e g 6 p b . 0 / l c d _ s e g 7 n c n c n c n c n c p e . 7 / l c d _ s e g 8 p e . 8 / l c d _ s e g 9 p e . 9 p e . 1 0 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 i c e _ d a t / p f . 0 p a . 1 2 n a n o 1 1 0 l q f p 1 2 8 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 l c d _ s e g 2 7 / p e . 1 3 l c d _ s e g 2 6 / / p b . 1 4 l c d _ s e g 2 5 / p b . 1 3 l c d _ s e g 1 9 / p d . 8 l c d _ s e g 1 8 / p d . 9 l c d _ s e g 1 7 / p d . 1 0 l c d _ s e g 1 6 / p d . 1 1 l c d _ s e g 1 5 / p d . 1 2 l c d _ s e g 1 4 / p d . 1 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 p e . 1 1 p e . 1 2 p d . 6 / l c d _ s e g 3 p b . 3 / l c d _ s e g 4 p c . 0 / l c d _ d h 1 p c . 1 / l c d _ d h 2 p c . 2 / l c d _ c o m 0 p c . 3 / l c d _ c o m 1 p c . 4 / l c d _ c o m 2 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p a . 1 p a . 0 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 p v s s l c d _ s e g 3 0 / p b . 8 l c d _ s e g 3 3 / p c . 1 5 l c d _ s e g 3 2 / p c . 1 4 l c d _ s e g 3 1 / p b . 1 5 n c x t 1 _ i n x t 1 _ o u t p c . 7 n c v d d n c v s s v s s v s s v s s 3 2 3 1 3 0 2 9 2 8 2 7 2 6 v l c d p e . 6 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 9 / l c d _ v 3 p b . 1 0 / l c d _ v 2 p b . 1 1 / l c d _ v 1 p e . 5 n c 6 5 6 6 6 7 6 8 6 9 7 0 7 1 p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 v r e f n c a d 8 / p d . 0 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 a d 9 / p d . 1 a d 1 0 / p d . 2 a d 1 1 / p d . 3 a v d d 9 7 n c
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 41 of 160 revision 1.0 8 nano100 series datasheet 3.3.2.2 numicro ? nano110 lqfp 64 - pin figure 3 ? 6 numicro ? nano110 lqfp 64 - pin diagram l c d _ s e g 2 0 / a d 5 / p a . 5 l c d _ s e g 1 9 / a d 6 / p a . 6 v r e f l c d _ s e g 1 2 / p b . 1 4 l c d _ s e g 1 1 / p b . 1 3 l c d _ s g e 1 0 / p b . 1 2 x 3 2 i x 3 2 o l c d _ s g e 9 / p a . 1 1 l c d _ s g e 8 / p a . 1 0 l c d _ s g e 7 / p a . 9 l c d _ s g e 6 / p a . 8 l c d _ s g e 5 / p b . 4 l c d _ s g e 4 / p b . 5 l c d _ s g e 3 / p b . 6 l c d _ s g e 2 / p b . 7 l d o _ c a p v d d v s s l c d _ s e g 1 7 / p c . 7 p c . 6 l c d _ s e g 1 6 / p c . 1 5 l c d _ s e g 1 5 / p c . 1 4 l c d _ s e g 1 4 / p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t l c d _ s e g 1 3 / p b . 8 p a . 4 / a d 4 / l c d _ s e g 2 1 p a . 3 / a d 3 / l c d _ s e g 2 2 p a . 2 / a d 2 / l c d _ s e g 2 3 p a . 1 / a d 1 p a . 0 / a d 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 / l c d _ s e g 2 4 p a . 1 3 / l c d _ s e g 2 5 p a . 1 4 / l c d _ s e g 2 6 p a . 1 5 / l c d _ s e g 2 7 p c . 8 / l c d _ s e g 2 8 p c . 9 / l c d _ s e g 2 9 a v d d v s s v d d p v s s p c . 0 / l c d _ d h 1 p c . 1 / l c d _ d h 2 p c . 2 / l c d _ c o m 0 p c . 3 / l c d _ c o m 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / l c d _ s e g 3 0 p c . 1 1 / l c d _ s e g 3 1 p b . 9 / l c d _ v 3 p b . 1 0 / l c d _ v 2 p b . 1 1 / l c d _ v 1 l c d _ v l c d p d . 1 5 p d . 1 4 p d . 7 p d . 6 p b . 3 / l c d _ c o m 2 p b . 2 / l c d _ c o m 3 p b . 1 / l c d _ s e g 0 ( c o m 4 ) p b . 0 / l c d _ s e g 1 ( c o m 5 ) n a n o 1 1 0 l q f p 6 4 - p i n
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 42 of 160 revision 1.0 8 nano100 series datasheet 3.3.3 numicro ? nano120 pin diagrams 3.3.3.1 numicro ? nano120 lqfp 128 - pin figure 3 ? 7 numicro ? nano120 lqfp 128 - pin diagram n c p d . 4 p d . 5 p b . 1 2 x 3 2 o n c x 3 2 i p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 n c l d o _ c a p n c n c n r e s e t v s s v s s n c v d d n c p f . 4 p e . 1 4 p a . 7 p a . 6 p a . 5 p a . 4 p a . 3 p a . 2 a v s s a v s s v s s v s s n c v d d n c i c e _ c l k / p f . 1 p c . 6 p f . 5 v s s p e . 1 5 p c . 5 p d . 1 5 p d . 1 4 p d . 7 p b . 2 p b . 1 p b . 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s n c p e . 7 p e . 8 p e . 9 p e . 1 0 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 i c e _ d a t / p f . 0 p a . 1 2 n a n o 1 2 0 l q f p 1 2 8 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 3 p b . 1 4 p b . 1 3 p d . 8 p d . 9 p d . 1 0 p d . 1 1 p d . 1 2 p d . 1 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 p e . 1 1 p e . 1 2 p d . 6 p b . 3 p c . 0 p c . 1 p c . 2 p c . 3 p c . 4 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p a . 1 p a . 0 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 p v s s p b . 8 p c . 1 5 p c . 1 4 p b . 1 5 n c x t 1 _ i n x t 1 _ o u t p c . 7 n c v d d n c v s s v s s v s s v s s 3 2 3 1 3 0 2 9 2 8 2 7 2 6 n c p e . 6 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 9 p b . 1 0 p b . 1 1 p e . 5 n c 6 5 6 6 6 7 6 8 6 9 7 0 7 1 p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 v r e f n c p d . 0 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 p d . 1 p d . 2 p d . 3 a v d d 9 7 n c
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 43 of 160 revision 1.0 8 nano100 series datasheet 3.3.3.2 numicro ? nano120 lqfp 64 - pin figure 3 ? 8 numicro ? nano120 lqfp 64 - pin diagram p a . 5 p a . 6 v r e f p b . 1 4 p b . 1 3 p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 p b . 6 p b . 7 l d o v d d v s s p c . 7 p c . 6 p c . 1 5 p c . 1 4 p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 a v d d v s s v d d p v s s p c . 0 p c . 1 p c . 2 p c . 3 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 p c . 1 1 p b . 9 p b . 1 0 p b . 1 1 p e . 5 p b . 3 p b . 2 p b . 1 p b . 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s n a n o 1 2 0 l q f p 6 4 - p i n
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 44 of 160 revision 1.0 8 nano100 series datasheet 3.3.3.3 numicro ? nano120 lqfp 48 - pin figure 3 ? 9 numicro ? nano120 lqfp 48 - pin diagram p a . 5 p a . 6 v r e f p b . 1 2 x 3 2 i x 3 2 o p a . 1 1 p a . 1 0 p a . 9 p a . 8 p b . 4 p b . 5 l d o _ c a p v d d v s s p c . 7 p c . 6 p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t p b . 8 p a . 4 p a . 3 p a . 2 p a . 1 p a . 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 p a . 1 3 p a . 1 4 p a . 1 5 a v d d p v s s 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n a n o 1 2 0 l q f p 4 8 - p i n p c . 0 p c . 1 p c . 2 p c . 3 p b . 3 p b . 2 p b . 1 p b . 0 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 45 of 160 revision 1.0 8 nano100 series datasheet 3.3.4 numicro ? nano130 pin diagrams 3.3.4.1 numicro ? nano130 lqfp 128 - pin figure 3 ? 10 numicro ? nano130 lqfp 128 - pin diagram n c l c d _ s e g 3 5 / p d . 4 l c d _ s e g 3 4 / p d . 5 l c d _ s e g 2 4 / p b . 1 2 x 3 2 o n c x 3 2 i l c d _ s e g 2 3 / p a . 1 1 l c d _ s e g 2 2 / p a . 1 0 l c d _ s e g 2 1 / p a . 9 l c d _ s e g 2 0 / p a . 8 l c d _ s e t 1 3 / p b . 4 l c d _ s e g 1 2 / p b . 5 l c d _ s e g 1 1 / p b . 6 l c d _ s e g 1 0 / p b . 7 n c l d o n c n c n r e s e t v s s v s s n c v d d n c p f . 4 l c d _ s e g 2 8 / p e . 1 4 p a . 7 / a d 7 / l c d _ s e g 3 6 p a . 6 / a d 6 / l c d _ s e g 3 7 p a . 5 / a d 5 / l c d _ s e g 3 8 p a . 4 / a d 4 / l c d _ s e g 3 9 p a . 3 / a d 3 p a . 2 / a d 2 a v s s a v s s v s s v s s n c v d d n c i c e _ c l k / p f . 1 p c . 6 p f . 5 v s s l c d _ s e g 2 9 / p e . 1 5 p c . 5 / l c d _ c o m 3 p d . 1 5 / l c d _ s e g 0 ( c o m 4 ) p d . 1 4 / l c d _ s e g 1 ( c o m 5 ) p d . 7 / l c d _ s e g 2 p b . 2 / l c d _ s e g 5 p b . 1 / l c d _ s e g 6 p b . 0 / l c d _ s e g 7 u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s n c p e . 7 / l c d _ s e g 8 p e . 8 / l c d _ s e g 9 p e . 9 p e . 1 0 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 i c e _ d a t / p f . 0 p a . 1 2 n a n o 1 3 0 l q f p 1 2 8 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 l c d _ s e g 2 7 / p e . 1 3 l c d _ s e g 2 6 / p b . 1 4 l c d _ s e g 2 5 / p b . 1 3 l c d _ s e g 1 9 / p d . 8 l c d _ s e g 1 8 / p d . 9 l c d _ s e g 1 7 / p d . 1 0 l c d _ s e g 1 6 / p d . 1 1 l c d _ s e g 1 5 / p d . 1 2 l c d _ s e g 1 4 / p d . 1 3 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 p e . 1 1 p e . 1 2 p d . 6 / l c d _ s e g 3 p b . 3 / l c d _ s e g 4 p c . 0 / l c d _ d h 1 p c . 1 / l c d _ d h 2 p c . 2 / l c d _ c o m 0 p c . 3 / l c d _ c o m 1 p c . 4 / l c d _ c o m 2 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p a . 1 / a d 1 p a . 0 / a d 0 p a . 1 3 p a . 1 4 p a . 1 5 p c . 8 p c . 9 p c . 1 0 p c . 1 1 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 p v s s l c d _ s e g 3 0 / p b . 8 l c d _ s e g 3 3 / p c . 1 5 l c d _ s e g 3 2 / p c . 1 4 l c d _ s e g 3 1 / p b . 1 5 n c x t 1 _ i n x t 1 _ o u t p c . 7 n c v d d n c v s s v s s v s s v s s 3 2 3 1 3 0 2 9 2 8 2 7 2 6 v l c d p e . 6 5 8 5 9 6 0 6 1 6 2 6 3 6 4 p b . 9 / l c d _ v 3 p b . 1 0 / l c d _ v 2 p b . 1 1 / l c d _ v 1 p e . 5 n c 6 5 6 6 6 7 6 8 6 9 7 0 7 1 p c . 1 2 p c . 1 3 p e . 0 p e . 1 p e . 2 p e . 3 p e . 4 v r e f n c a d 8 / p d . 0 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 a d 9 / p d . 1 a d 1 0 / p d . 2 a d 1 1 / p d . 3 a v d d 9 7 n c
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 46 of 160 revision 1.0 8 nano100 series datasheet 3.3.4.2 numicro ? nano130 lqfp 64 - pin figure 3 ? 11 numicro ? nano130 lqfp 64 - pin diagram l c d _ s e g 2 0 / a d 5 / p a . 5 l c d _ s e g 1 9 / a d 6 / p a . 6 v r e f l c d _ s e g 1 2 / p b . 1 4 l c d _ s e g 1 1 / p b . 1 3 l c d _ s g e 1 0 / p b . 1 2 x 3 2 i x 3 2 o l c d _ s g e 9 / p a . 1 1 l c d _ s g e 8 / p a . 1 0 l c d _ s g e 7 / p a . 9 l c d _ s g e 6 / p a . 8 l c d _ s g e 5 / p b . 4 l c d _ s g e 4 / p b . 5 l c d _ s g e 3 / p b . 6 l c d _ s g e 2 / p b . 7 l d o _ c a p v d d v s s l c d _ s e g 1 7 / p c . 7 p c . 6 l c d _ s e g 1 6 / p c . 1 5 l c d _ s e g 1 5 / p c . 1 4 l c d _ s e g 1 4 / p b . 1 5 x t 1 _ i n x t 1 _ o u t n r e s e t l c d _ s e g 1 3 / p b . 8 p a . 4 / a d 4 / l c d _ s e g 2 1 p a . 3 / a d 3 / l c d _ s e g 2 2 p a . 2 / a d 2 / l c d _ s e g 2 3 p a . 1 / a d 1 p a . 0 / a d 0 a v s s i c e _ c l k / p f . 1 i c e _ d a t / p f . 0 p a . 1 2 / l c d _ s e g 2 4 p a . 1 3 / l c d _ s e g 2 5 p a . 1 4 / l c d _ s e g 2 6 p a . 1 5 / l c d _ s e g 2 7 p c . 8 / l c d _ s e g 2 8 p c . 9 / l c d _ s e g 2 9 a v d d v s s v d d p v s s p c . 0 / l c d _ d h 1 p c . 1 / l c d _ d h 2 p c . 2 / l c d _ c o m 0 p c . 3 / l c d _ c o m 1 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / l c d _ s e g 3 0 p c . 1 1 / l c d _ s e g 3 1 p b . 9 / l c d _ v 3 p b . 1 0 / l c d _ v 2 p b . 1 1 / l c d _ v 1 v l c d p b . 3 / l c d _ c o m 2 p b . 2 / l c d _ c o m 3 p b . 1 / l c d _ s e g 0 ( c o m 4 ) p b . 0 / l c d _ s e g 1 ( c o m 5 ) u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s n a n o 1 3 0 l q f p 6 4 - p i n
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 47 of 160 revision 1.0 8 nano100 series datasheet 3.4 pin description 3.4.1 numicro ? nano100 pin description pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin 1 pe.13 i/o general purpose digital i/o pin 2 1 pb.14 i/o general purpose digital i/o pin int0 i external interrupt0 input pin sc2_cd i smartcard2 card detect pin spi2_ss1 i/o spi2 2 nd slave select pin 3 2 pb.13 i/o general purpose digital i/o pin ebi_ad1 i/o ebi address/data bus bit1 4 3 1 pb.12 i/o general purpose digital i/o pin ebi_ad0 i/o ebi address/data bus bit0 fclko o frequency divider output pin 5 nc 6 4 2 x32o o external 32.768 khz crystal output pin 7 5 3 x32i i external 32.768 khz crystal input pin 8 nc 9 6 4 pa.11 i/o general purpose digital i/o pin i2c1_scl i/o i 2 c1 clock pin ebi_nrd o ebi read enable output pin sc0_rst o smartcard0 rst pin sp i 2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin 10 7 5 pa.10 i/o general purpose digital i/o pin i2c1_sda i/o i 2 c1 data i/o pin ebi_nwr o ebi write enable output pin sc0_pwr o smartcard0 power pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin 11 8 6 pa.9 i/o general purpose digital i/o pin i2c0_scl i/o i 2 c0 clock pin sc0_dat i/o smartcard0 data pin(sc0_uart_rxd) spi2_clk i/o spi2 serial clock pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 48 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin 12 9 7 pa.8 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin sc0_clk o smartcard0 clock pin(sc0_uart_txd) spi2_ss0 i/o spi2 1 st slave select pin 13 pd.8 i/o general purpose digital i/o pin 14 pd.9 i/o general purpose digital i/o pin 15 pd.10 i/o general purpose digital i/o pin 16 pd.11 i/o general purpose digital i/o pin 17 pd.12 i/o general purpose digital i/o pin 18 pd.13 i/o general purpose digital i/o pin 19 10 8 pb.4 i/o general purpose digital i/o pin uart1_rxd i uart1 data receiver input pin sc0_cd i smartcard0 card detect pin spi2_ss0 i/o spi2 1 st slave select pin 20 11 9 pb.5 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin sc0_rst o smartcard0 rst pin spi2_clk i/o spi2 serial clock pin 21 12 pb.6 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin ebi_ale o ebi address latch enable output pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin 22 13 pb.7 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin ebi_ncs o ebi chip select enable output pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin 23 nc 24 14 10 ldo_cap p ldo output pin 25 nc 26 nc
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 49 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin 27 15 11 vdd p power supply for i/o ports and ldo source 28 nc 29 16 12 vss p ground 30 vss p ground 31 vss p ground 32 vss p ground 33 pe.12 i/o general purpose digital i/o pin 34 pe.11 i/o general purpose digital i/o pin 35 pe.10 i/o general purpose digital i/o pin 36 pe.9 i/o general purpose digital i/o pin 37 pe.8 i/o general purpose digital i/o pin 38 pe.7 i/o general purpose digital i/o pin 39 nc 40 nc 41 nc 42 nc 43 nc 44 17 13 pb.0 i/o general purpose digital i/o pin uart0_rxd i uart0 data receiver input pin spi1_mosi0 i/o spi1 1 st mosi (master out, slave in) pin 45 18 14 pb.1 i/o general purpose digital i/o pin uart0_txd o uart0 data transmitter output pin spi1_miso0 i/o spi1 1 st miso (master in, slave out) pin 46 19 15 pb.2 i/o general purpose digital i/o pin uart0_rtsn o uart0 request to send output pin ebi_nwrl o ebi low byte write enable output pin spi1_clk i/o spi1 serial clock pin 47 20 16 pb.3 i/o general purpose digital i/o pin uart0_ctsn i uart0 clear to send input pin ebi_nwrh o ebi high byte write enable output pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 50 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin spi1_ss0 i/o spi1 1 st slave select pin 48 21 pd.6 i/o general purpose digital i/o pin 49 22 pd.7 i/o general purpose digital i/o pin 50 23 pd.14 i/o general purpose digital i/o pin 51 24 pd.15 i/o general purpose digital i/o pin 52 pc.5 i/o general purpose digital i/o pin spi0_mosi1 i/o spi0 2 nd mosi (master out, slave in) pin 53 pc.4 i/o general purpose digital i/o pin spi0_miso1 i/o spi0 2 nd miso (master in, slave out) pin 54 25 17 pc.3 i/o general purpose digital i/o pin spi0_mosi0 i/ o spi0 1 st mosi (master out, slave in) pin i2s_do o i 2 s data output sc1_rst o smartcard1 rst pin 55 26 18 pc.2 i/o general purpose digital i/o pin spi 0 _miso0 i /o spi 0 1 st miso (master in, slave out) pin i2s_di i i 2 s data input sc1_pwr o smartcard1 pwr pin 56 27 19 pc.1 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin i2s_bclk i/o i 2 s bit clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) 57 28 20 pc.0 / mclko i/o general purpose digital i/o pin / module c lock o utput pin spi0_ss0 i/o spi0 1 st slave select pin i2s_lrclk i/o i 2 s left right channel clock sc1_clk o smartcard1 clock pin(sc1_uart_txd) 58 pe.6 i/o general purpose digital i/o pin 59 nc 60 nc 61 29 21 pe.5 i/o general purpose digital i/o pin pwm1_ch1 i/o pwm1 channel1 output
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 51 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin 62 30 22 pb.11 i/o general purpose digital i/o pin pwm1_ch0 i/o pwm1 channel0 output tm3 o timer3 external counter input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 63 31 23 pb.10 i/o general purpose digital i/o pin spi0_ss1 i/o spi0 2 nd slave select pin tm2 o timer2 external counter input sc2_clk o smartcard2 clock pin(sc2_uart_txd) spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 64 32 24 pb.9 i/o general purpose digital i/o pin spi1_ss1 i/o spi1 2 nd slave select pin tm1 o timer1 external counter input sc2_rst o smartcard2 rst pin int0 i external interrupt0 input pin 65 pe.4 i/o general purpose digital i/o pin spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 66 pe.3 i/o general purpose digital i/o pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 67 pe.2 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin 68 pe.1 i/o general purpose digital i/o pin. pwm1_ch3 i/o pwm1 channel3 output spi0_ss0 i/o spi0 1 st slave select pin 69 pe.0 i/o general purpose digital i/o pin pwm1_ch2 i/o pwm1 channel2 output i2s_mclk o i 2 s master clock output pin 70 pc.13 i/o general purpose digital i/o pin spi1_mosi1 i/o spi1 2 nd mosi (master out, slave in) pin pwm1_ch1 o pwm1 channel1 output
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 52 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin snooper i snooper pin int 1 i external interrupt 1 i2c0_scl o i 2 c0 clock pin 71 pc.12 i/o general purpose digital i/o pin spi 1 _miso1 i/o spi 1 2 nd miso (master in, slave out) pin pwm1_ch0 o pwm1 channel0 output int0 i external interrupt0 input pin i2c0_sda i/o i 2 c0 data i/o pin 72 33 pc.11 i/o general purpose digital i/o pin spi1_mosi0 i/ o spi1 1 st mosi (master out, slave in) pin uart1_txd o uart1 data transmitter output pin 73 34 pc.10 i/o general purpose digital i/o pin spi1_miso0 i /o spi1 1 st miso (master in, slave out) pin uart1_rxd i uart1 data receiver input pin 74 35 pc.9 i/o general purpose digital i/o pin spi1_clk i/o spi1 serial clock pin i2c1_scl i/o i 2 c1 clock pin 75 36 pc.8 i/o general purpose digital i/o pin spi1_ss0 i/o spi1 1 st slave select pin ebi_mclk o ebi external clock output pin i2c1_sda i/o i 2 c1 data i/o pin 76 37 25 pa.15 i/o general purpose digital i/o pin pwm0_ch3 i/o pwm0 channel3 output i2s_mclk o i 2 s master clock output pin tc3 i timer3 capture input sc0_pwr o smartcard0 power pin uart0_txd o uart0 data transmitter output pin 77 38 26 pa.14 i/o general purpose digital i/o pin pwm0_ch2 i/o pwm0 channel2 output ebi_ad15 i/o ebi address/data bus bit15
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 53 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin tc2 i timer2 capture input uart0_rxd i uart0 data receiver input pin 78 39 27 pa.13 i/o general purpose digital i/o pin pwm0_ch1 i/o pwm0 channel1 output ebi_ad14 i/o ebi address/data bus bit14 tc1 i timer1 capture input i2c0_scl i/o i 2 c0 clock pin 79 40 28 pa.12 i/o general purpose digital i/o pin pwm0_ch0 i/o pwm0 channel0 output ebi_ad13 i/o ebi address/data bus bit13 tc0 i timer0 capture input i2c0_sda i/o i 2 c0 data i/o pin 80 41 29 ice_dat i/o serial wired debugger data pin pf.0 i/o general purpose digital i/o pin int0 i external interrupt0 input pin 81 42 30 ice_clk i serial wired debugger clock pin pf.1 i/o general purpose digital i/o pin fclko o frequency divider output pin int1 i external interrupt1 input pin 82 nc 83 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 84 nc 85 vss p ground 86 vss p ground 87 43 31 avss ap ground pin for analog circuit 88 avss ap ground pin for analog circuit 89 44 32 pa.0 i/o general purpose digital i/o pin ad0 ai adc analog input0 sc2_cd i smartcard2 card detect 90 45 33 pa.1 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 54 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin ad1 ai adc analog input1 ebi_ad12 i/o ebi address/data bus bit12 91 46 34 pa.2 i/o general purpose digital i/o pin ad2 ai adc analog input2 ebi_ad11 i/o ebi address/data bus bit11 uart1_rxd i uart1 data receiver input pin 92 47 35 pa.3 i/o general purpose digital i/o pin ad3 ai adc analog input3 ebi_ad10 i/o ebi address/data bus bit10 uart1_txd o uart1 data transmitter output pin 93 48 36 pa.4 i/o general purpose digital i/o pin ad4 ai adc analog input4 ebi_ad9 i/o ebi address/data bus bit9 sc2_pwr o smartcard2 power pin i2c0_sda i/o i 2 c0 data i/o pin 94 49 37 pa.5 i/o general purpose digital i/o pin ad5 ai adc analog input5 ebi_ad8 i/o ebi address/data bus bit8 sc2_rst o smartcard2 rst pin i2c0_scl i/o i 2 c0 clock pin 95 50 38 pa.6 i/o general purpose digital i/o pin ad6 ai adc analog input6 ebi_ad7 i/o ebi address/data bus bit7 tc3 i timer3 capture input sc2_clk o smartcard2 clock pin(sc2_uart_txd) pwm0_ch3 o pwm0 channel3 output 96 pa.7 i/o general purpose digital i/o pin ad7 ai adc analog input7 ebi_ad6 i/o ebi address/data bus bit6 tc2 i timer2 capture input
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 55 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) pwm0_ch2 o pwm0 channel2 output 97 51 39 vref ap voltage reference input for adc 98 nc 99 52 40 avdd ap power supply for internal analog circuit 100 pd.0 i/o general purpose digital i/o pin uart1_rxd i uart1 data receiver input pin spi2_ss0 i/o spi2 1 st slave select pin sc1_clk o smartcard1 clock pin(sc1_uart_txd) ad8 ai adc analog input8 101 pd.1 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin spi2_clk i/o spi2 serial clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd). ad9 ai adc analog input9 102 pd.2 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin i2s_lrclk i/o i 2 s left right channel clock spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin sc1_pwr o smartcard1 power pin ad10 ai adc analog input10 103 pd.3 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin i2s_bclk i/o i 2 s bit clock pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin sc1_rst o smartcard1 rst pin ad11 ai adc analog input11 104 nc 105 pd.4 i/o general purpose digital i/o pin i2s_di i i 2 s data input
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 56 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin spi2_miso1 i/o spi2 2 nd miso (master in, slave out) pin sc1_cd i smartcard1 card detect 106 pd.5 i/o general purpose digital i/o pin i2s_do o i 2 s data output spi2_mosi1 i/o spi2 2 nd mosi (master out, slave in) pin 107 53 41 pc.7 i/o general purpose digital i/o pin da1_out ao dac 1 output ebi_ad5 i/o ebi address/data bus bit5 tc1 i timer1 capture input pwm0_ch1 o pwm1 channel1 output 108 54 42 pc.6 i/o general purpose digital i/o pin da0_out i dac0 output ebi_ad4 i/o ebi address/data bus bit4 tc0 i timer0 capture input sc1_cd i smartcard1 card detect pin pwm0_ch0 o pwm0 channel0 output 109 55 pc.15 i/o general purpose digital i/o pin ebi_ad3 i/o ebi address/data bus bit3 tc0 i timer0 capture input pwm1_ch2 o pwm1 channel1 output 110 56 pc.14 i/o general purpose digital i/o pin ebi_ad2 i/o ebi address/data bus bit2 pwm1_ch3 i/o pwm1 channel3 output 111 57 43 pb.15 i/o general purpose digital i/o pin int1 i external interrupt1 input pin snooper i snooper pin sc1_cd i smartcard1 card detect 112 nc 113 58 44 xt1_in o external 4~24 mhz crystal output pin p f . 3 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 57 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp /qfn 48 - pin 114 59 45 xt1_out i external 4~24 mhz crystal input pin p f . 2 i/o general purpose digital i/o pin 115 nc 116 60 46 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 117 61 vss p ground 118 vss p ground 119 nc 120 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 121 nc 122 pf.4 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin 123 pf.5 i/o general purpose digital i/o pin i2c0_scl i/o i 2 c0 clock pin 124 vss p ground 125 63 47 pvss p pll ground 126 64 48 pb.8 i/o general purpose digital i/o pin stadc i adc external trigger input. tm0 i timer0 external counter input int0 i external interrupt0 input pin sc2_pwr o smartcard2 power pin 127 pe.15 i/o general purpose digital i/o pin 128 pe.14 i/o general purpose digital i/o pin note: pin type: i = digital input, o = digital output; ai = analog input; ao = analog output; p = power pin; ap = analog power.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 58 of 160 revision 1.0 8 nano100 series datasheet 3.4.2 numicro ? nano110 pin description pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.13 i/o general purpose digital i/o pin lcd_seg27 o lcd segment output 27 at lqfp128 2 1 pb.14 i/o general purpose digital i/o pin int0 i external interrupt0 input pin sc2_cd i smartcard2 card detect spi2_ss1 i/o spi2 2 nd slave select pin lcd_seg12 o lcd segment output 12 at lqfp64 lcd_seg26 o lcd segment output 26 at lqfp128 3 2 pb.13 i/o general purpose digital i/o pin ebi_ad1 i/o ebi address/data bus bit1 lcd_seg11 o lcd segment output 11 at lqfp64 lcd_seg25 o lcd segment output 25 at lqfp128 4 3 pb.12 i/o general purpose digital i/o pin ebi_ad0 i/o ebi address/data bus bit0 fclko o frequency divider output pin lcd_seg10 o lcd segment output 10 at lqfp64 lcd_seg24 o lcd segment output 24 at lqfp128 5 nc 6 4 x32o o external 32.768 khz crystal output pin 7 5 x32i i external 32.768 khz crystal input pin 8 nc 9 6 pa.11 i/o general purpose digital i/o pin i2c1_scl i/o i 2 c1 clock pin ebi_nrd o ebi read enable output pin sc0_rst o smartcard0 rst pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin lcd_seg9 o lcd segment output 9 at lqfp64 lcd_seg23 o lcd segment output 23 at lqfp128 10 7 pa.10 i/o general purpose digital i/o pin i2c1_sda i/o i 2 c1 data i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 59 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin ebi_nwr o ebi write enable output pin sc0_pwr o smartcard0 power pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin lcd_seg8 o lcd segment output 8 at lqfp64 lcd_seg22 o lcd segment output 22 at lqfp128 11 8 pa.9 i/o general purpose digital i/o pin i2c0_scl i/o i 2 c0 clock pin sc0_dat i/o smartcard0 data pin(sc0_uart_rxd) spi2_clk i/o spi2 serial clock pin lcd_seg7 o lcd segment output 7 at lqfp64 lcd_seg21 o lcd segment output 21 at lqfp128 12 9 pa.8 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin sc0_clk o smartcard0 clock pin(sc0_uart_txd) spi2_ss0 i/o spi2 1 st slave select pin lcd_seg6 o lcd segment output 6 at lqfp64 lcd_seg20 o lcd segment output 20 at lqfp128 13 pd.8 i/o general purpose digital i/o pin lcd_seg19 o lcd segment output 19 at lqfp128 14 pd.9 i/o general purpose digital i/o pin lcd_seg18 o lcd segment output 18 at lqfp128 15 pd.10 i/o general purpose digital i/o pin lcd_seg17 o lcd segment output 17 at lqfp128 16 pd.11 i/o general purpose digital i/o pin lcd_seg16 o lcd segment output 16 at lqfp128 17 pd.12 i/o general purpose digital i/o pin lcd_seg15 o lcd segment output 15 at lqfp128 18 pd.13 i/o general purpose digital i/o pin lcd_seg14 o lcd segment output 14 at lqfp128 19 10 pb.4 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 60 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin uart1_rxd i uart1 data receiver input pin sc0_cd i smartcard0 card detect pin spi2_ss0 i/o spi2 1 st slave select pin lcd_seg5 o lcd segment output 5 at lqfp64 lcd_seg13 o lcd segment output 13 at lqfp128 20 11 pb.5 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin sc0_rst o smartcard0 rst pin spi2_clk i/o spi2 serial clock pin lcd_seg4 o lcd segment output 4 at lqfp64 lcd_seg12 o lcd segment output 12 at lqfp128 21 12 pb.6 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin ebi_ale o ebi address latch enable output pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin lcd_seg3 o lcd segment output 3 at lqfp64 lcd_seg11 o lcd segment output 11 at lqfp128 22 13 pb.7 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin ebi_ncs o ebi chip select enable output pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin lcd_seg2 o lcd segment output 2 at lqfp64 lcd_seg10 o lcd segment output 10 at lqfp128 23 nc 24 14 ldo_cap p ldo output pin 25 nc 26 nc 27 15 vdd p power supply for i/o ports and ldo source 28 nc 29 16 vss p ground
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 61 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 30 vss p ground 31 vss p ground 32 vss p ground 33 pe.12 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin 34 pe.11 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin 35 pe.10 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin 36 pe.9 i/o general purpose digital i/o pin uart1_rxd i uart1 data receiver input pin 37 pe.8 i/o general purpose digital i/o pin lcd_seg9 o lcd segment output 9 at lqfp128 38 pe.7 i/o general purpose digital i/o pin lcd_seg8 o lcd segment output 8 at lqfp128 39 nc 40 nc 41 nc 42 nc 43 nc 44 17 pb.0 i/o general purpose digital i/o pin uart0_rxd i uart0 data receiver input pin spi1_mosi0 i/o spi1 1 st mosi (master out, slave in) pin lcd_seg1 o lcd segment output 1 at lqfp64 (or as ld_com5) lcd_seg7 o lcd segment output 7 at lqfp128 45 18 pb.1 i/o general purpose digital i/o pin uart0_txd o uart0 data transmitter output pin spi1_miso0 i/o spi1 1 st miso (master in, slave out) pin lcd_seg0 o lcd segment output 0 at lqfp64 (or as lcd_com4)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 62 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin lcd_seg6 o lcd segment output 6 at lqfp128 46 19 pb.2 i/o general purpose digital i/o pin uart0_rtsn o uart0 request to send output pin ebi_nwrl o ebi low byte write enable output pin spi1_clk i/o spi1 serial clock pin lcd_com3 o lcd common output 3 at lqfp64 lcd_seg5 o lcd segment output 5 at lqfp128 47 20 pb.3 i/o general purpose digital i/o pin uart0_ctsn i uart0 clear to send input pin ebi_nwrh o ebi high byte write enable output pin spi1_ss0 i/o spi1 1 st slave select pin lcd_com2 o lcd common output 2 at lqfp64 lcd_seg4 o lcd segment output 4 at lqfp128 48 21 pd.6 i/o general purpose digital i/o pin lcd_seg3 o lcd segment output 3 at lqfp128 49 22 pd.7 i/o general purpose digital i/o pin lcd_seg2 o lcd segment output 2 at lqfp128 50 23 pd.14 i/o general purpose digital i/o pin lcd_seg1 o lcd segment output 1 at lqfp128 (or as lcd_com5) 51 24 pd.15 i/o general purpose digital i/o pin lcd_seg0 o lcd segment output 0 at lqfp128 (or as lcd_com4) 52 pc.5 i/o general purpose digital i/o pin spi0_mosi1 i/o spi0 2 nd mosi (master out, slave in) pin lcd_com3 o lcd common output 3 at lqfp128 53 pc.4 i/o general purpose digital i/o pin spi0_miso1 i/o spi0 2 nd miso (master in, slave out) pin lcd_com2 o lcd common output 2 at lqfp128 54 25 pc.3 i/o general purpose digital i/o pin spi0_mosi0 i/ o spi0 1 st mosi (master out, slave in) pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 63 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin i2s_do o i 2 s data output sc1_rst o smartcard1 rst pin lcd_com1 o lcd common output 1 at lqfp64 lcd_com1 o lcd common output 1 at lqfp128 55 26 pc.2 i/o general purpose digital i/o pin spi0_miso0 i /o spi0 1 st miso (master in, slave out) pin i2s_di i i 2 s data input sc1_pwr o smartcard1 pwr pin lcd_com0 o lcd common output 0 at lqfp64 lcd_com0 o lcd common output 0 at lqfp128 56 27 pc.1 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin i2s_bclk i/o i 2 s bit clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) lcd_dh2 o lcd externl capacitor pin of charge pump circuit at lqfp64 lcd_dh2 o lcd externl capacitor pin of charge pump circuit at lqfp128 57 28 pc.0 / mclko i/o general purpose digital i/o pin / module c lock o utput pin spi0_ss0 i/o spi0 1 st slave select pin i2s_lrclk i/o i 2 s left right channel clock sc1_clk o smartcard1 clock pin(sc1_uart_txd) lcd_dh1 o lcd externl capacitor pin of charge pump circuit at lqfp64 lcd_dh1 o lcd externl capacitor pin of charge pump circuit at lqfp128 58 pe.6 i/o general purpose digital i/o pin 59 29 lcd_vlcd ao lcd power supply pin 60 nc 61 pe.5 i/o general purpose digital i/o pin 62 30 pb.11 i/o general purpose digital i/o pin pwm1_ch0 i/o pwm1 channel0 output
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 64 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin tm3 o timer3 external counter input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin lcd_v1 o unit voltage for lcd charge pump circuit at lqfp64 lcd_v1 o lcd unit voltage for lcd charge pump circuit at lqfp128 63 31 pb.10 i/o general purpose digital i/o pin spi0_ss1 i/o spi0 2 nd slave select pin tm2 o timer2 external counter input sc2_clk o smartcard2 clock pin(sc2_uart_txd) spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin lcd_v2 o lcd driver biasing voltage at lqfp64 lcd_v2 o lcd driver biasing voltage at lqfp128 64 32 pb.9 i/o general purpose digital i/o pin spi1_ss1 i/o spi1 2 nd slave select pin tm1 o timer1 external counter input sc2_rst o smartcard2 rst pin int0 i external interrupt0 input pin lcd_v3 o lcd driver biasing voltage at lqfp64 lcd_v3 o lcd driver biasing voltage at lqfp128 65 pe.4 i/o general purpose digital i/o pin spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 66 pe.3 i/o general purpose digital i/o pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 67 pe.2 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin 68 pe.1 i/o general purpose digital i/o pin pwm1_ch3 i/o pwm1 channel3 output spi0_ss0 i/o spi0 1 st slave select pin 69 pe.0 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 65 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin pwm1_ch2 i/o pwm1 channel2 output i2s_mclk o i 2 s master clock output pin 70 pc.13 i/o general purpose digital i/o pin spi1_mosi1 i/o spi1 2 nd mosi (master out, slave in) pin pwm1_ch1 o pwm1 channel1 output snooper i snooper pin int 1 i external interrupt 1 i2c0_scl o i 2 c0 clock pin 71 pc.12 i/o general purpose digital i/o pin spi1_miso1 i /o spi1 2 nd miso (master in, slave out) pin pwm1_ch0 o pwm1 channel0 output int0 i external interrupt0 input pin i2c0_sda i/o i 2 c0 data i/o pin 72 33 pc.11 i/o general purpose digital i/o pin spi1_mosi0 i/ o spi1 1 st mosi (master out, slave in) pin uart1_txd o uart1 data transmitter output pin lcd_seg31 o lcd segment output 31 at lqfp64 73 34 pc.10 i/o general purpose digital i/o pin spi1_miso0 i /o spi1 1 st miso (master in, slave out) pin uart1_rxd i uart1 data receiver input pin lcd_seg30 o lcd segment output 30 at lqfp64 74 35 pc.9 i/o general purpose digital i/o pin spi1_clk i/o spi1 serial clock pin i2c1_scl i/o i 2 c1 clock pin lcd_seg29 o lcd segment output 29 at lqfp64 75 36 pc.8 i/o general purpose digital i/o pin spi1_ss0 i/o spi1 1 st slave select pin ebi_mclk o ebi external clock output pin i2c1_sda i/o i 2 c1 data i/o pin lcd_seg28 o lcd segment output 28 at lqfp64
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 66 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 76 37 pa.15 i/o general purpose digital i/o pin pwm0_ch3 i/o pwm0 channel3 output i2s_mclk o i 2 s master clock output pin tc3 i timer3 capture input sc0_pwr o smartcard0 power pin uart0_txd o uart0 data transmitter output pin lcd_seg27 o lcd segment output 27 at lqfp64 77 38 pa.14 i/o general purpose digital i/o pin pwm0_ch2 i/o pwm0 channel2 output ebi_ad15 i/o ebi address/data bus bit15 tc2 i timer2 capture input uart0_rxd i uart0 data receiver input pin lcd_seg26 o lcd segment output 26 at lqfp64 78 39 pa.13 i/o general purpose digital i/o pin pwm0_ch1 i/o pwm0 channel1 output ebi_ad14 i/o ebi address/data bus bit14 tc1 i timer1 capture input i2c0_scl i/o i 2 c0 clock pin lcd_seg25 o lcd segment output 25 at lqfp64 79 40 pa.12 i/o general purpose digital i/o pin pwm0_ch0 i/o pwm0 channel0 output ebi_ad13 i/o ebi address/data bus bit13 tc0 i timer0 capture input i2c0_sda i/o i 2 c0 data i/o pin lcd_seg24 o lcd segment output 24 at lqfp64 80 41 ice_dat i/o serial wired debugger data pin pf.0 i/o general purpose digital i/o pin int0 i external interrupt0 input pin 81 42 ice_clk i serial wired debugger clock pin pf.1 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 67 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin fclko o frequency divider output pin int1 i external interrupt1 input pin 82 nc 83 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 84 nc 85 vss p ground 86 vss p ground 87 43 avss ap ground pin for analog circuit 88 avss ap ground pin for analog circuit 89 44 pa.0 i/o general purpose digital i/o pin ad0 ai adc analog input0 sc2_cd i smartcard2 card detect 90 45 pa.1 i/o general purpose digital i/o pin ad1 ai adc analog input1 ebi_ad12 i/o ebi address/data bus bit12 91 46 pa.2 i/o general purpose digital i/o pin ad2 ai adc analog input2 ebi_ad11 i/o ebi address/data bus bit11 uart1_rxd i uart1 data receiver input pin lcd_seg23 * ao lcd segment output 23 at lqfp64 92 47 pa.3 i/o general purpose digital i/o pin ad3 ai adc analog input3 ebi_ad10 i/o ebi address/data bus bit10 uart1_txd o uart1 data transmitter output pin lcd_seg22 * ao lcd segment output 22 at lqfp64 93 48 pa.4 i/o general purpose digital i/o pin ad4 ai adc analog input4 ebi_ad9 i/o ebi address/data bus bit9 sc2_pwr o smartcard2 power pin i2c0_sda i/o i 2 c0 data i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 68 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin lcd_seg21 * ao lcd segment output 21 at lqfp64 lcd_seg39 * ao lcd segment output 39 at lqfp128 94 49 pa.5 i/o general purpose digital i/o pin ad5 ai adc analog input5 ebi_ad8 i/o ebi address/data bus bit8 sc2_rst o smartcard2 rst pin i2c0_scl i/o i 2 c0 clock pin lcd_seg20 * ao lcd segment output 19 at lqfp64 lcd_seg38 * ao lcd segment output 37 at lqfp128 95 50 pa.6 i/o general purpose digital i/o pin ad6 ai adc analog input6 ebi_ad7 i/o ebi address/data bus bit7 tc3 i timer3 capture input sc2_clk o smartcard2 clock pin(sc2_uart_txd) pwm0_ch3 o pwm0 channel3 output lcd_seg19 * ao lcd segment output 19 at lqfp64 lcd_seg37 * ao lcd segment output 37 at lqfp128 96 pa.7 i/o general purpose digital i/o pin ad7 ai adc analog input7 ebi_ad6 i/o ebi address/data bus bit6 tc2 i timer2 capture input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) pwm0_ch2 o pwm0 channel2 output lcd_seg36 * ao lcd segment output 36 output at lqfp128 97 51 vref ap voltage reference input for adc 98 nc 99 52 avdd ap power supply for internal analog circuit 100 pd.0 i/o general purpose digital i/o pin uart1_rxd i uart1 data receiver input pin spi2_ss0 i/o spi2 1 st slave select pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 69 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin sc1_clk o smartcard1 clock pin(sc1_uart_txd) ad8 ai adc analog input8 101 pd.1 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin spi2_clk i/o spi2 serial clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) ad9 ai adc analog input9 102 pd.2 i/o general purpose digital i/o pin uart1_rtsn uart1 request to send output pin i2s_lrclk i/o i 2 s left right channel clock spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin sc1_pwr o smartcard1 power pin ad10 ai adc analog input10 103 pd.3 i/o general purpose digital i/o pin uart1_ctsn uart1 clear to send input pin i2s_bclk i/o i 2 s bit clock pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin sc1_rst o smartcard1 rst pin ad11 ai adc analog input11 104 nc 105 pd.4 i/o general purpose digital i/o pin i2s_di i i 2 s data input spi2_miso1 i/o spi2 2 nd miso (master in, slave out) pin sc1_cd i smartcard1 card detect lcd_seg35 ao lcd segment output 35 at lqfp10 106 pd.5 i/o general purpose digital i/o pin i2s_do o i 2 s data output spi2_mosi1 i/o spi2 2 nd mosi (master out, slave in) pin lcd_seg34 ao lcd segment output 34 at lqfp128 107 53 pc.7 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 7 0 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin da1_out ao dac 1 output ebi_ad5 i/o ebi address/data bus bit5 tc1 i timer1 capture input pwm0_ch1 o pwm1 channel1 output lcd_seg17 * ao lcd segment output 17 at lqfp64 108 54 pc.6 i/o general purpose digital i/o pin da0_out i dac0 output ebi_ad4 i/o ebi address/data bus bit4 tc0 i timer0 capture input sc1_cd i smartcard1 card detect pin pwm0_ch0 o pwm0 channel0 output 109 55 pc.15 i/o general purpose digital i/o pin ebi_ad3 i/o ebi address/data bus bit3 tc0 i timer0 capture input pwm1_ch2 o pwm1 channel1 output lcd_seg16 ao lcd segment output 16 at lqfp64 lcd_seg33 ao lcd segment output 33 at lqfp128 110 56 pc.14 i/o general purpose digital i/o pin ebi_ad2 i/o ebi address/data bus bit2 pwm1_ch3 i/o pwm1 channel3 output lcd_seg15 ao lcd segment output 15 at lqfp64 lcd_seg32 ao lcd segment output 32 at lqfp128 111 57 pb.15 i/o general purpose digital i/o pin int1 i external interrupt1 input pin snooper i snooper pin lcd_seg14 ao lcd segment output 14 at lqfp64 lcd_seg31 ao lcd segment output 31 at lqfp128 112 nc 113 58 xt1_in o external 4~24 mhz crystal output pin p f . 3 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 71 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 114 59 xt1_out i external 4~24 mhz crystal input pin p f . 2 i/o general purpose digital i/o pin 115 nc 116 60 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 117 61 vss p ground 118 vss p ground 119 nc 120 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 121 nc 122 pf.4 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin 123 pf.5 i/o general purpose digital i/o pin i2c0_scl i/o i 2 c0 clock pin 124 vss p ground 125 63 pvss p pll ground 126 64 pb.8 i/o general purpose digital i/o pin stadc i adc external trigger input. tm0 i timer0 external counter input int0 i external interrupt0 input pin sc2_pwr o smartcard2 power pin lcd_seg13 ao lcd segment output 13 at lqfp64 lcd_seg30 ao lcd segment output 30 at lqfp128 127 pe.15 i/o general purpose digital i/o pin lcd_seg29 o lcd segment output 29 at lqfp128 128 pe.14 i/o general purpose digital i/o pin lcd_seg28 o lcd segment output 28 at lqfp128 note: 1. pin type: i = digital input, o=digital output; ai=analog input; ao= analog output; p=power pin; ap=analog power; 2. * : output voltage for adc/lcd shared pins cannot be higher than vdd because these pins are without 5v tolerance.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 72 of 160 revision 1.0 8 nano100 series datasheet 3.4.3 numicro ? nano120 pin description pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 1 pe.13 i/o general purpose digital io pin 2 1 pb.14 i/o general purpose digital io pin int0 i external interrupt0 input pin sc2_cd i smartcard2 card detect spi2_ss1 i/o spi2 2 nd slave select pin 3 2 pb.13 i/o general purpose digital io pin ebi_ad1 i/o ebi address/data bus bit1 4 3 1 pb.12 i/o general purpose digital io pin ebi_ad0 i/o ebi address/data bus bit0 fclko o frequency divider output pin 5 nc 6 4 2 x32o o external 32.768 khz crystal output pin 7 5 3 x32i i external 32.768 khz crystal input pin 8 nc 9 6 4 pa.11 i/o general purpose digital io pin i2c1_scl i/o i 2 c 1 clock pin ebi_nrd o ebi read enable output pin sc0_rst o smartcard0 rst pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin 10 7 5 pa.10 i/o general purpose digital io pin i2c1_sda i/o i 2 c 1 data i/o pin ebi_nwr o ebi write enable output pin sc0_pwr o smartcard0 power pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin 11 8 6 pa.9 i/o general purpose digital io pin i2c0_scl i/o i 2 c 0 clock pin sc0_dat i/o smartcard0 data pin(sc0_uart_rxd) spi2_clk i/o spi2 serial clock pin 12 9 7 pa.8 i/o general purpose digital io pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 73 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 i2c0_sda i/o i 2 c 0 data i/o pin sc0_clk o smartcard0 clock pin(sc0_uart_txd) spi2_ss0 i/o spi2 1 st slave select pin 13 pd.8 i/o general purpose digital io pin 14 pd.9 i/o general purpose digital io pin 15 pd.10 i/o general purpose digital io pin 16 pd.11 i/o general purpose digital io pin 17 pd.12 i/o general purpose digital io pin 18 pd.13 i/o general purpose digital io pin 19 10 8 pb.4 i/o general purpose digital io pin uart1_rxd i uart1 data receiver input pin sc0_cd i smartcard0 card detect pin spi2_ss0 i/o spi2 1 st slave select pin 20 11 9 pb.5 i/o general purpose digital io pin uart1_txd o uart1 data transmitter output pin sc0_rst o smartcard0 rst pin spi2_clk i/o spi2 serial clock pin 21 12 pb.6 i/o general purpose digital io pin uart1_nrts o uart1 request to send output pin ebi_ale o ebi address latch enable output pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin 22 13 pb.7 i/o general purpose digital io pin uart1_ncts i uart1 clear to send input pin ebi_ncs o ebi chip select enable output pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin 23 nc 24 14 10 ldo_cap p ldo output pin 25 nc 26 nc 27 15 11 vdd p power supply for i/o ports and ldo source
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 74 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 28 nc 29 16 12 vss p ground 30 vss p ground 31 vss p ground 32 vss p ground 33 pe.12 i/o general purpose digital io pin 34 pe.11 i/o general purpose digital io pin 35 pe.10 i/o general purpose digital io pin 36 pe.9 i/o general purpose digital io pin 37 pe.8 i/o general purpose digital io pin 38 pe.7 i/o general purpose digital io pin 39 nc 40 17 13 usb_vbus usb power supply: from usb host or hub. 41 18 14 usb_vdd33_c ap usb internal power regulator output 3.3v decoupling pin 42 19 15 usb_d - usb usb differential signal d - 43 20 16 usb_d+ usb usb differential signal d+ 44 21 17 pb.0 i/o general purpose digital io pin uart0_rxd i uart0 data receiver input pin spi1_mosi0 i/o spi1 1 st mosi (master out, slave in) pin 45 22 18 pb.1 i/o general purpose digital io pin uart0_txd o uart0 data transmitter output pin spi1_miso0 i/o spi1 1 st miso (master in, slave out) pin 46 23 19 pb.2 i/o general purpose digital io pin uart0_nrts o uart0 request to send output pin ebi_nwrl o ebi low byte write enable output pin spi1_clk i/o spi1 serial clock pin 47 24 20 pb.3 i/o general purpose digital io pin uart0_ncts i uart0 clear to send input pin ebi_nwrh o ebi high byte write enable output pin spi1_ss0 i/o spi1 1 st slave select pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 75 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 48 pd.6 i/o general purpose digital io pin 49 pd.7 i/o general purpose digital io pin 50 pd.14 i/o general purpose digital io pin 51 pd.15 i/o general purpose digital io pin 52 pc.5 i/o general purpose digital io pin spi0_mosi1 i/o spi0 2 nd mosi (master out, slave in) pin 53 pc.4 i/o general purpose digital io pin spi0_miso1 i/o spi0 2 nd miso (master in, slave out) pin 54 25 21 pc.3 i/o general purpose digital io pin spi0_mosi0 i/ o spi0 1 st mosi (master out, slave in) pin i2s_do o i 2 s data output sc1_rst o smartcard1 rst pin 55 26 22 pc.2 i/o general purpose digital io pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin i2s_di i i 2 s data input sc1_pwr o smartcard1 pwr pin 56 27 23 pc.1 i/o general purpose digital io pin spi0_clk i/o spi0 serial clock pin i2s_bclk i/o i 2 s bit clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) 57 28 24 pc.0 / mclko i/o general purpose digital io pin / module c lock o utput pin spi0_ss0 i/o spi0 1 st slave select pin i2s_lrclk i/o i 2 s left right channel clock sc1_clk o smartcard1 clock pin(sc1_uart_txd) 58 pe.6 i/o general purpose digital io pin 59 nc 60 nc 61 29 pe.5 i/o general purpose digital io pin pwm1_ch1 i/o pwm1 channel1 output 62 30 pb.11 i/o general purpose digital io pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 76 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 pwm1_ch0 i/o pwm1 channel0 output tm3 o timer3 external counter input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 63 31 pb.10 i/o general purpose digital io pin spi0_ss1 i/o spi0 2 nd slave select pin tm2 o timer2 external counter input sc2_clk o smartcard2 clock pin(sc2_uart_txd) spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 64 32 pb.9 i/o general purpose digital io pin spi1_ss1 i/o spi1 2 nd slave select pin tm1 o timer1 external counter input sc2_rst o smartcard2 rst pin int0 i external interrupt0 input pin 65 pe.4 i/o general purpose digital io pin spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 66 pe.3 i/o general purpose digital io pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 67 pe.2 i/o general purpose digital io pin spi0_clk i/o spi0 serial clock pin 68 pe.1 i/o general purpose digital io pin pwm1_ch3 i/o pwm1 channel3 output spi0_ss0 i/o spi0 1 st slave select pin 69 pe.0 i/o general purpose digital io pin pwm1_ch2 i/o pwm1 channel2 output i2s_mclk o i 2 s master clock output pin 70 pc.13 i/o general purpose digital io pin spi1_mosi1 i/o spi1 2 nd mosi (master out, slave in) pin pwm1_ch 1 o pwm1 channel1 output snooper i snooper pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 77 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 int 1 i external interrupt 1 input pin i2c0_scl o i 2 c 0 clock pin 71 pc.12 i/o general purpose digital io pin spi1_miso1 i /o spi1 2 nd miso (master in, slave out) pin pwm1_ch0 o pwm1 channel 0 output int0 i external interrupt 0 input pin i2c0_sda i/o i 2 c 0 data i/o pin 72 33 pc.11 i/o general purpose digital io pin spi1_mosi0 i/ o spi1 1 st mosi (master out, slave in) pin uart1_txd o uart1 data transmitter output pin 73 34 pc.10 i/o general purpose digital io pin spi1_miso0 i /o spi1 1 st miso (master in, slave out) pin uart1_rxd i uart1 data receiver input pin 74 35 pc.9 i/o general purpose digital io pin spi1_clk i/o spi1 serial clock pin i2c1_scl i/o i 2 c 1 clock pin 75 36 pc.8 i/o general purpose digital io pin spi1_ss0 i/o spi1 1 st slave select pin ebi_mclk o ebi external clock output pin i2c1_sda i/o i 2 c 1 data i/o pin 76 37 25 pa.15 i/o general purpose digital io pin pwm0_ch3 i/o pwm0 channel3 output i2s_mclk o i 2 s master clock output pin tc3 i timer3 capture input sc0_pwr o smartcard0 power pin uart0_txd o uart0 data transmitter output pin 77 38 26 pa.14 i/o general purpose digital io pin pwm0_ch2 i/o pwm0 channel2 output ebi_ad15 i/o ebi address/data bus bit15 tc2 i timer 2 capture input
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 78 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 uart0_rxd i uart0 data receiver input pin 78 39 27 pa.13 i/o general purpose digital io pin pwm0_ch1 i/o pwm0 channel1 output ebi_ad14 i/o ebi address/data bus bit14 tc1 i timer1 capture input i2c0_scl i/o i 2 c 0 clock pin 79 40 28 pa.12 i/o general purpose digital io pin pwm0_ch0 i/o pwm0 channel0 output ebi_ad13 i/o ebi address/data bus bit13 tc0 i timer 0 capture input i2c0_sda i/o i 2 c 0 data i/o pin 80 41 29 ice_dat i/o serial wired debugger data pin pf.0 i/o general purpose digital io pin int0 i external interrupt0 input pin 81 42 30 ice_clk i serial wired debugger clock pin pf.1 i/o general purpose digital io pin fclko o frequency divider output pin int1 i external interrupt1 input pin 82 nc 83 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 84 nc 85 vss p ground 86 vss p ground 87 43 31 avss ap ground pin for analog circuit 88 avss ap ground pin for analog circuit 89 44 32 pa.0 i/o general purpose digital io pin ad0 ai adc analog input0 sc2_cd i smartcard2 card detect 90 45 33 pa.1 i/o general purpose digital io pin ad1 ai adc analog input1
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 79 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 ebi_ad12 i/o ebi address/data bus bit12 91 46 34 pa.2 i/o general purpose digital io pin ad2 ai adc analog input2 ebi_ad11 i/o ebi address/data bus bit11 uart1_rx d i uart1 data receiver input pin 92 47 35 pa.3 i/o general purpose digital io pin ad3 ai adc analog input3 ebi_ad10 i/o ebi address/data bus bit10 uart1_txd o uart1 data transmitter output pin 93 48 36 pa.4 i/o digital gpio pin ad4 ai adc analog input4 ebi_ad9 i/o ebi address/data bus bit9 sc2_pwr o smartcard2 power pin i2c0_sda i/o i 2 c 0 data i/o pin 94 49 37 pa.5 i/o general purpose digital io pin ad5 ai adc analog input5 ebi_ad8 i/o ebi address/data bus bit8 sc2_rst o smartcard2 rst pin i2c0_scl i/o i 2 c 0 clock pin 95 50 38 pa.6 i/o general purpose digital io pin ad6 ai adc analog input6 ebi_ad7 i/o ebi address/data bus bit7 tc3 i timer3 capture input sc2_clk o smartcard2 clock pin(sc2_uart_txd) pwm0_ch3 o pwm0 channel3 output 96 pa.7 i/o general purpose digital io pin ad7 ai adc analog input7 ebi_ad6 i/o ebi address/data bus bit6 tc2 i timer2 capture input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 80 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 pwm0_ch2 o pwm0 channel2 output 97 51 39 vref ap voltage reference input for adc 98 nc 99 52 40 avdd ap power supply for internal analog circuit 100 pd.0 i/o general purpose digital io pin uart1_rxd i uart1 data receiver input pin spi2_ss0 i/o spi2 1 st slave select pin sc1_clk o smartcard1 clock pin(sc1_uart_txd) ad8 ai adc analog input8 101 pd.1 i/o general purpose digital io pin uart1_txd o uart1 data transmitter output pin spi2_clk i/o spi2 serial clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) ad9 ai adc analog input9 102 pd.2 i/o general purpose digital io pin uart1_nrts o uart1 request to send output pin i2s_lrclk i/o i 2 s left right channel clock spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin sc1_pwr o smartcard1 power pin ad10 ai adc analog input10 103 pd.3 i/o general purpose digital io pin uart1_ncts i uart1 clear to send input pin i2s_bclk i/o i 2 s bit clock pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin sc1_rst o smartcard1 rst pin ad11 ai adc analog input11 104 nc 105 pd.4 i/o general purpose digital io pin i2s_di i i 2 s data input spi2_miso1 i/o spi2 2 nd miso (master in, slave out) pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 81 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 sc1_cd i smartcard1 card detect 106 pd.5 i/o general purpose digital io pin i2s_do o i 2 s data output spi2_mosi1 i/o spi2 2 nd mosi (master out, slave in) pin 107 53 41 pc.7 i/o general purpose digital io pin da1+out ao dac 1 output ebi_ad5 i/o ebi address/data bus bit5 tc1 i timer1 capture input pwm0_ch1 o pwm1 channel1 output 108 54 42 pc.6 i/o general purpose digital io pin da0_out i dac0 output ebi_ad4 i/o ebi address/data bus bit4 tc0 i timer 0 capture input sc1_cd smartcard1 card detect pin pwm0_ch0 o pwm0 channel0 output 109 55 pc.15 i/o general purpose digital io pin ebi_ad3 i/o ebi address/data bus bit3 tc0 i timer0 capture input pwm1_ch2 o pwm1 channel1 output 110 56 pc.14 i/o general purpose digital io pin ebi_ad2 i/o ebi address/data bus bit2 pwm1_ch3 i/o pwm1 channel3 output 111 57 43 pb.15 i/o general purpose digital io pin int1 i external interrupt1 input pin snooper i snooper pin sc1_cd i smartcard1 card detect 112 nc 113 58 44 xt1_in o external 4~24 mhz crystal output pin p f . 3 i/o general purpose digital i/o pin 114 59 45 xt1_out i external 4~24 mhz crystal input pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 82 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 lqfp 64 lqfp 48 p f . 2 i/o general purpose digital i/o pin 115 nc 116 60 46 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 117 61 vss p ground 118 vss p ground 119 nc 120 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 121 nc 122 pf.4 i/o general purpose digital io pin i2c0_sda i/o i 2 c 0 data i/o pin 123 pf.5 i/o general purpose digital io pin i2c0_scl i/o i 2 c 0 clock pin 124 vss p ground 125 63 47 pvss p pll ground 126 64 48 pb.8 i/o general purpose digital io pin stadc i adc external trigger input. tm0 i timer0 external counter input int0 i external interrupt0 input pin sc2_pwr o smartcard2 power pin 127 pe.15 i/o general purpose digital io pin 128 pe.14 i/o general purpose digital io pin note: 1. pin type: i = digital input, o=digital output; ai=analog input; ao= analog output; p=power pin; ap=analog power;
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 83 of 160 revision 1.0 8 nano100 series datasheet 3.4.4 numicro ? nano130 pin description pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.13 i/o general purpose digital i/o pin lcd_seg27 o lcd segment output 27 at lqfp128 2 1 pb.14 i/o general purpose digital i/o pin int0 i external interrupt0 input pin sc2_cd i smartcard2 card detect spi2_ss1 i/o spi2 2 nd slave select pin lcd_seg12 o lcd segment output 12 at lqfp64 lcd_seg26 o lcd segment output 26 at lqfp128 3 2 pb.13 i/o general purpose digital i/o pin ebi_ad1 i/o ebi address/data bus bit1 lcd_seg11 o lcd segment output 11 at lqfp64 lcd_seg25 o lcd segment output 25 at lqfp128 4 3 pb.12 i/o general purpose digital i/o pin ebi_ad0 i/o ebi address/data bus bit0 fclko o frequency divider output pin lcd_seg10 o lcd segment output 10 at lqfp64 lcd_seg24 o lcd segment output 24 at lqfp128 5 nc 6 4 x32o o external 32.768 khz crystal output pin 7 5 x32i i external 32.768 khz crystal input pin 8 nc 9 6 pa.11 i/o general purpose digital i/o pin i2c1_scl i/o i 2 c1 clock pin ebi_nrd o ebi read enable output pin sc0_rst o smartcard0 rst pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin lcd_seg9 o lcd segment output 9 at lqfp64 lcd_seg23 o lcd segment output 23 at lqfp128 10 7 pa.10 i/o general purpose digital i/o pin i2c1_sda i/o i 2 c1 data i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 84 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin ebi_nwr o ebi write enable output pin sc0_pwr o smartcard0 power pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin lcd_seg8 o lcd segment output 8 at lqfp64 lcd_seg22 o lcd segment output 22 at lqfp128 11 8 pa.9 i/o general purpose digital i/o pin i2c0_scl i/o i 2 c0 clock pin sc0_dat i/o smartcard0 data pin(sc0_uart_rxd) spi2_clk i/o spi2 serial clock pin lcd_seg7 o lcd segment output 7 at lqfp64 lcd_seg21 o lcd segment output 21 at lqfp128 12 9 pa.8 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin sc0_clk o smartcard0 clock pin(sc0_uart_txd) spi2_ss0 i/o spi2 1 st slave select pin lcd_seg6 o lcd segment output 6 at lqfp64 lcd_seg20 o lcd segment output 20 at lqfp128 13 pd.8 i/o general purpose digital i/o pin lcd_seg19 o lcd segment output 19 at lqfp128 14 pd.9 i/o general purpose digital i/o pin lcd_seg18 o lcd segment output 18 at lqfp128 15 pd.10 i/o general purpose digital i/o pin lcd_seg17 o lcd segment output 17 at lqfp128 16 pd.11 i/o general purpose digital i/o pin lcd_seg16 o lcd segment output 16 at lqfp128 17 pd.12 i/o general purpose digital i/o pin lcd_seg15 o lcd segment output 15 at lqfp128 18 pd.13 i/o general purpose digital i/o pin lcd_seg14 o lcd segment output 14 at lqfp128 19 10 pb.4 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 85 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin uart1_rxd i uart1 data receiver input pin sc0_cd i smartcard0 card detect pin spi2_ss0 i/o spi2 1 st slave select pin lcd_seg5 o lcd segment output 5 at lqfp64 lcd_seg13 o lcd segment output 13 at lqfp128 20 11 pb.5 i/o general purpose digital i/o pin uart1_txd o uart1 data transmitter output pin sc0_rst o smartcard0 rst pin spi2_clk i/o spi2 serial clock pin lcd_seg4 o lcd segment output 4 at lqfp64 lcd_seg12 o lcd segment output 12 at lqfp128 21 12 pb.6 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin ebi_ale o ebi address latch enable output pin spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin lcd_seg3 o lcd segment output 3 at lqfp64 lcd_seg11 o lcd segment output 11 at lqfp128 22 13 pb.7 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin ebi_ncs o ebi chip select enable output pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin lcd_seg2 o lcd segment output 2 at lqfp64 lcd_seg10 o lcd segment output 10 at lqfp128 23 nc 24 14 ldo_cap p ldo output pin 25 nc 26 nc 27 15 vdd p power supply for i/o ports and ldo source 28 nc 29 16 vss p ground
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 86 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 30 vss p ground 31 vss p ground 32 vss p ground 33 pe.12 i/o general purpose digital i/o pin 34 pe.11 i/o general purpose digital i/o pin 35 pe.10 i/o general purpose digital i/o pin 36 pe.9 i/o general purpose digital i/o pin 37 pe.8 i/o general purpose digital i/o pin lcd_seg9 o lcd segment output 9 at lqfp128 38 pe.7 i/o general purpose digital i/o pin lcd_seg8 o lcd segment output 8 at lqfp128 39 nc 40 17 usb_vbus usb power supply: from usb host or hub. 41 18 usb_vdd33_cap usb internal power regulator output 3.3v decoupling pin 42 19 usb_d - usb usb differential signal d - 43 20 usb_d+ usb usb differential signal d+ 44 21 pb.0 i/o general purpose digital i/o pin uart0_rxd i uart0 data receiver input pin spi1_mosi0 i/o spi1 1 st mosi (master out, slave in) pin lcd_seg1 o lcd segment output 1 at lqfp64 (or as lcd_com5) lcd_seg7 o lcd segment output 7 at lqfp128 45 22 pb.1 i/o general purpose digital i/o pin uart0_txd o uart0 data transmitter output pin spi1_miso0 i/o spi1 1 st miso (master in, slave out) pin lcd_seg0 o lcd segment output 0 at lqfp64 (or as lcd_com4) lcd_seg6 o lcd segment output 6 at lqfp128 46 23 pb.2 i/o general purpose digital i/o pin uart0_rtsn o uart0 request to send output pin ebi_nwrl o ebi low byte write enable output pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 87 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin spi1_clk i/o spi1 serial clock pin lcd_com3 o lcd common output 3 at lqfp64 lcd_seg5 o lcd segment output 5 at lqfp128 47 24 pb.3 i/o general purpose digital i/o pin uart0_ctsn i uart0 clear to send input pin ebi_nwrh o ebi high byte write enable output pin spi1_ss0 i/o spi1 1 st slave select pin lcd_com2 o lcd common output 2 at lqfp64 lcd_seg4 o lcd segment output 4 at lqfp128 48 pd.6 i/o general purpose digital i/o pin lcd_seg3 o lcd segment output 3 at lqfp128 49 pd.7 i/o general purpose digital i/o pin lcd_seg2 o lcd segment output 2 at lqfp128 50 pd.14 i/o general purpose digital i/o pin lcd_seg1 o lcd segment output 1 at lqfp128 (or as lcd_com5) 51 pd.15 i/o general purpose digital i/o pin lcd_seg0 o lcd segment output 0 at lqfp128 (or as lcd_com4) 52 pc.5 i/o general purpose digital i/o pin spi0_mosi1 i/o spi0 2 nd mosi (master out, slave in) pin lcd_com3 o lcd common output 3 at lqfp128 53 pc.4 i/o general purpose digital i/o pin spi0_miso1 i/o spi0 2 nd miso (master in, slave out) pin lcd_com2 o lcd common output 2 at lqfp128 54 25 pc.3 i/o general purpose digital i/o pin spi0_mosi0 i/ o spi0 1 st mosi (master out, slave in) pin i2s_do o i 2 s data output sc1_rst o smartcard1 rst pin lcd_com1 o lcd common output 1 at lqfp64 lcd_com1 o lcd common output 1 at lqfp128
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 88 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 55 26 pc.2 i/o general purpose digital i/o pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin i2s_di i i 2 s data input sc1_pwr o smartcard1 pwr pin lcd_com0 o lcd common output 0 at lqfp64 lcd_com0 o lcd common output 0 at lqfp128 56 27 pc.1 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin i2s_bclk i/o i 2 s bit clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) lcd_dh2 o lcd externl capacitor pin of charge pump circuit at lqfp64 lcd_dh2 o lcd externl capacitor pin of charge pump circuit at lqfp128 57 28 pc.0 / mclko i/o general purpose digital i/o pin / module c lock o utput pin spi0_ss0 i/o spi0 1 st slave select pin i2s_lrclk i/o i 2 s left right channel clock sc1_clk o smartcard1 clock pin(sc1_uart_txd) lcd_dh1 o lcd externl capacitor pin of charge pump circuit at lqfp64 lcd_dh1 o lcd externl capacitor pin of charge pump circuit at lqfp128 58 pe.6 i/o general purpose digital i/o pin 59 29 lcd_vlcd ao lcd power supply pin 60 nc 61 pe.5 general purpose digital i/o pin 62 30 pb.11 i/o general purpose digital i/o pin pwm1_ch0 i/o pwm1 channel0 output tm3 o timer3 external counter input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 89 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin lcd_v1 o lcd unit voltage for lcd charge pump circuit at lqfp64 lcd_v1 o lcd unit voltage for lcd charge pump circuit at lqfp128 63 31 pb.10 i/o general purpose digital i/o pin spi0_ss1 i/o spi0 2 nd slave select pin tm2 o timer2 external counter input sc2_clk o smartcard2 clock pin(sc2_uart_txd) spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin lcd_v2 o lcd driver biasing voltage at lqfp64 lcd_v2 o lcd driver biasing voltage at lqfp128 64 32 pb.9 i/o general purpose digital i/o pin spi1_ss1 i/o spi1 2 nd slave select pin tm1 o timer1 external counter input sc2_rst o smartcard2 rst pin int0 i external interrupt0 input pin lcd_v3 o lcd driver biasing voltage at lqfp64 lcd_v3 o lcd driver biasing voltage at lqfp128 65 pe.4 i/o general purpose digital i/o pin spi0_mosi0 i/o spi0 1 st mosi (master out, slave in) pin 66 pe.3 i/o general purpose digital i/o pin spi0_miso0 i/o spi0 1 st miso (master in, slave out) pin 67 pe.2 i/o general purpose digital i/o pin spi0_clk i/o spi0 serial clock pin 68 pe.1 i/o general purpose digital i/o pin pwm1_ch3 i/o pwm1 channel3 output spi0_ss0 i/o spi0 1 st slave select pin 69 pe.0 i/o general purpose digital i/o pin pwm1_ch2 i/o pwm1 channel2 output i2s_mclk o i 2 s master clock output pin 70 pc.13 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 90 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin spi1_mosi1 i/o spi1 2 nd mosi (master out, slave in) pin pwm1_ch1 o pwm1 channel1 output snooper i snooper pin int 1 i external interrupt 1 input pin i2c0_scl o i 2 c0 clock pin 71 pc.12 i/o general purpose digital i/o pin spi1_miso1 i /o spi1 2 nd miso (master in, slave out) pin pwm1_ch0 o pwm1 channel0 output int0 i external interrupt0 input pin i2c0_sda i/o i 2 c0 data i/o pin 72 33 pc.11 i/o general purpose digital i/o pin spi1_mosi0 i/ o spi1 1 st mosi (master out, slave in) pin uart1_txd o uart1 data transmitter output pin lcd_seg31 o lcd segment output 31 at lqfp64 73 34 pc.10 i/o general purpose digital i/o pin spi1_miso0 i /o spi1 1 st miso (master in, slave out) pin uart1_rxd i uart1 data receiver input pin lcd_seg30 o lcd segment output 30 at lqfp64 74 35 pc.9 i/o general purpose digital i/o pin spi1_clk i/o spi1 serial clock pin i2c1_scl i/o i 2 c1 clock pin lcd_seg29 o lcd segment output 29 at lqfp64 75 36 pc.8 i/o general purpose digital i/o pin spi1_ss0 i/o spi1 1 st slave select pin ebi_mclk o ebi external clock output pin i2c1_sda i/o i 2 c1 data i/o pin lcd_seg28 o lcd segment output 28 at lqfp64 76 37 pa.15 i/o general purpose digital i/o pin pwm0_ch3 i/o pwm0 channel3 output i2s_mclk o i 2 s master clock output pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 91 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin tc3 i timer3 capture input sc0_pwr o smartcard0 power pin uart0_txd o uart0 data transmitter output pin lcd_seg27 o lcd segment output 27 at lqfp64 77 38 pa.14 i/o general purpose digital i/o pin pwm0_ch2 i/o pwm0 channel2 output ebi_ad15 i/o ebi address/data bus bit15 tc2 i timer2 capture input uart0_rxd i uart0 data receiver input pin lcd_seg26 o lcd segment output 26 at lqfp64 78 39 pa.13 i/o general purpose digital i/o pin pwm0_ch1 i/o pwm0 channel1 output ebi_ad14 i/o ebi address/data bus bit14 tc1 i timer1 capture input i2c0_scl i/o i 2 c0 clock pin lcd_seg25 o lcd segment output 25 at lqfp64 79 40 pa.12 i/o general purpose digital i/o pin pwm0_ch0 i/o pwm0 channel0 output ebi_ad13 i/o ebi address/data bus bit13 tc0 i timer0 capture input i2c0_sda i/o i 2 c0 data i/o pin lcd_seg24 o lcd segment output 24 at lqfp64 80 41 ice_dat i/o serial wired debugger data pin pf.0 i/o general purpose digital i/o pin int0 i external interrupt0 input pin 81 42 ice_clk i serial wired debugger clock pin pf.1 i/o general purpose digital i/o pin fclko o frequency divider output pin int1 i external interrupt1 input pin 82 nc
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 92 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 83 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 84 nc 85 vss p ground 86 vss p ground 87 43 avss ap ground pin for analog circuit 88 avss ap ground pin for analog circuit 89 44 pa.0 i/o general purpose digital i/o pin ad0 ai adc analog input0 sc2_cd i smartcard2 card detect 90 45 pa.1 i/o general purpose digital i/o pin ad1 ai adc analog input1 ebi_ad12 i/o ebi address/data bus bit12 91 46 pa.2 i/o general purpose digital i/o pin ad2 ai adc analog input2 ebi_ad11 i/o ebi address/data bus bit11 uart1_rxd i uart1 data receiver input pin lcd_seg23 * ao lcd segment output 23 at lqfp64 92 47 pa.3 i/o general purpose digital i/o pin ad3 ai adc analog input3 ebi_ad10 i/o ebi address/data bus bit10 uart1_txd o uart1 data transmitter output pin lcd_seg22 * ao lcd segment output 22 at lqfp64 93 48 pa.4 i/o general purpose digital i/o pin ad4 ai adc analog input4 ebi_ad9 i/o ebi address/data bus bit9 sc2_pwr o smartcard2 power pin i2c0_sda i/o i 2 c0 data i/o pin lcd_seg21 * ao lcd segment output 21 at lqfp64 lcd_seg39 * ao lcd segment output 39 at lqfp128 94 49 pa.5 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 93 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin ad5 ai adc analog input5 ebi_ad8 i/o ebi address/data bus bit8 sc2_rst o smartcard2 rst pin i2c0_scl i/o i 2 c0 clock pin lcd_seg20 * ao lcd segment output 20 at lqfp64 lcd_seg38 * ao lcd segment output 38 at lqfp128 95 50 pa.6 i/o general purpose digital i/o pin ad6 ai adc analog input6 ebi_ad7 i/o ebi address/data bus bit7 tc3 i timer3 capture input sc2_clk o smartcard2 clock pin(sc2_uart_txd) pwm0_ch3 o pwm0 channel3 output lcd_seg19 * ao lcd segment output 19 at lqfp64 lcd_seg37 * ao lcd segment output 37 at lqfp128 96 pa.7 i/o general purpose digital i/o pin ad7 ai adc analog input7 ebi_ad6 i/o ebi address/data bus bit6 tc2 i timer2 capture input sc2_dat i/o smartcard2 data pin(sc2_uart_rxd) pwm0_ch2 o pwm0 channel2 output lcd_seg36 * ao lcd segment output 36 output at lqfp128 97 51 vref ap voltage reference input for adc 98 nc 99 52 avdd ap power supply for internal analog circuit 100 pd.0 i/o general purpose digital i/o pin uart1_rxd i uart1 data receiver input pin spi2_ss0 i/o spi2 1 st slave select pin sc1_clk o smartcard1 clock pin(sc1_uart_txd) ad8 ai adc analog input8 101 pd.1 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 94 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin tx1 o uart1 data transmitter output pin spi2_clk i/o spi2 serial clock pin sc1_dat i/o smartcard1 data pin(sc1_uart_rxd) ad9 ai adc analog input9 102 pd.2 i/o general purpose digital i/o pin uart1_rtsn o uart1 request to send output pin i2s_lrclk i/o i 2 s left right channel clock spi2_miso0 i/o spi2 1 st miso (master in, slave out) pin sc1_pwr o smartcard1 power pin ad10 ai adc analog input10 103 pd.3 i/o general purpose digital i/o pin uart1_ctsn i uart1 clear to send input pin i2s_bclk i/o i 2 s bit clock pin spi2_mosi0 i/o spi2 1 st mosi (master out, slave in) pin sc1_rst o smartcard1 rst pin ad11 ai adc analog input11 104 nc 105 pd.4 i/o general purpose digital i/o pin i2s_di i i 2 s data input spi2_miso1 i/o spi2 2 nd miso (master in, slave out) pin sc1_cd i smartcard1 card detect lcd_seg35 ao lcd segment output 35 at lqfp128 106 pd.5 i/o general purpose digital i/o pin i2s_do o i 2 s data output spi2_mosi1 i/o spi2 2 nd mosi (master out, slave in) pin lcd_seg34 ao lcd segment output 34 at lqfp128 107 53 pc.7 i/o general purpose digital i/o pin da1_out ao dac 1 output ebi_ad5 i/o ebi address/data bus bit5 tc1 i timer1 capture input
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 95 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin pwm0_ch1 o pwm1 channel1 output lcd_seg17 * ao lcd segment output 17 at lqfp64 108 54 pc.6 i/o general purpose digital i/o pin da0_out i dac0 output ebi_ad4 i/o ebi address/data bus bit4 tc0 i timer0 capture input sc1_cd smartcard1 card detect pin pwm0_ch0 o pwm0 channel0 output 109 55 pc.15 i/o general purpose digital i/o pin ebi_ad3 i/o ebi address/data bus bit3 tc0 i timer0 capture input pwm1_ch2 o pwm1 channel1 output lcd_seg16 ao lcd segment output 16 at lqfp64 lcd_seg33 ao lcd segment output 33 at lqfp128 110 56 pc.14 i/o general purpose digital i/o pin ebi_ad2 i/o ebi address/data bus bit2 pwm1_ch3 i/o pwm1 channel3 output lcd_seg15 ao lcd segment output 15 at lqfp64 lcd_seg32 ao lcd segment output 32 at lqfp128 111 57 pb.15 i/o general purpose digital i/o pin int1 i external interrupt1 input pin snooper i snooper pin sc1_cd i smartcard1 card detect lcd_seg14 ao lcd segment output 14 at lqfp64 lcd_seg31 ao lcd segment output 31 at lqfp128 112 nc 113 58 xt1_in o external 4~24 mhz crystal output pin p f . 3 i/o general purpose digital i/o pin 114 59 xt1_out i external 4~24 mhz crystal input pin p f . 2 i/o general purpose digital i/o pin
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 96 of 160 revision 1.0 8 nano100 series datasheet pin no. pin name pin type description lqfp 128 - pin lqfp 64 - pin lqfp 48 - pin 115 nc 116 60 nreset i external reset input: low active, set this pin low reset chip to initial state. with internal pull - up. 117 61 vss p ground 118 vss p ground 119 nc 120 62 vdd p power supply for i/o ports and ldo source for internal pll and digital circuit 121 nc 122 pf.4 i/o general purpose digital i/o pin i2c0_sda i/o i 2 c0 data i/o pin 123 pf.5 i/o digital gpi/o pin i2c0_scl i/o i 2 c0 clock pin 124 vss p ground 125 63 pvss i/o pll ground 126 64 pb.8 i/o general purpose digital i/o pin stadc i adc external trigger input. tm0 i timer0 external counter input int0 i external interrupt0 input pin sc2_pwr o smartcard2 power pin lcd_seg13 ao lcd segment output 13 at lqfp64 lcd_seg30 ao lcd segment output 30 at lqfp128 127 pe.15 i/o general purpose digital i/o pin lcd_seg29 o lcd segment output 29 at lqfp128 128 pe.14 i/o general purpose digital i/o pin lcd_seg28 o lcd segment output 28 at lqfp128 note: 1. pin type: i=digital input, o=digital output; ai=analog input; ao=analog output; p=power pin; ap=analog power 2. * : output voltage for adc/lcd shared pins cannot be higher than vdd because these pins are without 5v tolerance.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 97 of 160 revision 1.0 8 nano100 series datasheet 4 block diagram 4.1 nano100 block diagram figure 4 ? 1 numicro ? nano100 block diagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 1 2 3 / 6 4 / 3 2 k b c o r t e x - m 0 4 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c 1 . 8 / 2 . 5 v r e f 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 / u a r t 3 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e - u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 / u a r t 4 g p i o a , b , c , d , e , f p l l h x t l x t h i r c l i r c 1 2 - b a d c 1 2 - b d a c s c 2 / u a r t 5
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 98 of 160 revision 1.0 8 nano100 series datasheet 4.2 nano110 block diagram figure 4 ? 2 numicro ? nano110 block diagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 1 2 3 / 6 4 / 3 2 k b c o r t e x - m 0 4 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c l c d 1 . 8 / 2 . 5 v r e f l c d c o m / s e g u p t o 4 x 4 0 / 6 x 3 8 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 / u a r t 3 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e - u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 / u a r t 4 g p i o a , b , c , d , e , f l c d b o o s t e r p l l h x t l x t h i r c l i r c 1 2 - b a d c 1 2 - b d a c s c 2 / u a r t 5
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 99 of 160 revision 1.0 8 nano100 series datasheet 4.3 nano120 block diagram figure 4 ? 3 numicro ? nano120 block diagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 1 2 3 / 6 4 / 3 2 k b c o r t e x - m 0 4 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c u s b - 5 1 2 b u s b p h y 1 . 8 / 2 . 5 v r e f 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 / u a r t 3 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e - u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 / u a r t 4 g p i o a , b , c , d , e , f p l l h x t l x t h i r c l i r c 1 2 - b a d c 1 2 - b d a c s c 2 / u a r t 5
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 100 of 160 revision 1.0 8 nano100 series datasheet 4.4 nano130 block diagram figure 4 ? 4 numicro ? nano130 block diagram p e r i p h e r a l s w i t h p d m a e b i f l a s h 1 2 3 / 6 4 / 3 2 k b c o r t e x - m 0 4 2 m h z d m a c l k _ c t l i s p 4 k b s r a m 1 6 / 8 k b p w m 1 t i m e r 2 / 3 u a r t 1 s p i 1 i 2 s i 2 c 1 i 2 c 0 p w m 0 t i m e r 0 / 1 u a r t 0 s p i 0 s p i 2 r t c l c d u s b - 5 1 2 b u s b p h y 1 . 8 / 2 . 5 v r e f l c d c o m / s e g u p t o 4 x 4 0 / 6 x 3 8 1 . 8 v l d o ( i n p u t : 1 . 8 ~ 3 . 6 v ) p o r ( 1 . 8 v ) b o d ( 1 . 7 / 2 . 0 / 2 . 5 v ) s c 0 / u a r t 3 t e m p s e n s o r w d t p e r i p h e r a l s w i t h w a k e u p n o t e : b o d c a n w a k e u p s y s t e m . e x t e r n a l i n t e r r u p t s , i n c l u d e d i n g p i o , c a n w a k e u p s y s t e m , t o o . s c 1 / u a r t 4 g p i o a , b , c , d , e , f l c d b o o s t e r p l l h x t l x t h i r c l i r c 1 2 - b a d c 1 2 - b d a c s c 2 / u a r t 5
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 101 of 160 revision 1.0 8 nano100 series datasheet 5 functional descripti on 5.1 memory organization 5.1.1 overview the nano100 provides 4g - byte addressing space. the memory locations assigned to each on - chip modules are shown in following. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip module. the nano100 series only supports little - endian data format. 5.1.2 memory map the memory locations assigned to each on - chip controllers are shown in the following table. address space token modules flash & sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128kb) 0x2000_0000 C 0x2000_3fff sram_ba sram memory space (16kb) 0x6000_0000 --- 0x6001_ffff extmem_ba external memory space(128kb) ahb modules space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system management control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff dma_ba dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 C 0x5001_03ff ebi_ba external bus interface control registers apb1 modules space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr01_ba timer0 and timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwm0_ba pwm0 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb fs device controller registers 0x400a_0000 C 0x400a_3fff dac_ba digital - analog - converter (dac) control registers 0x400b_0000 C 0x400b_3fff lcd_ba lcd control registers 0x400d_0000 C 0x400d_3fff spi2_ba spi2 with master/slave function control registers
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 102 of 160 revision 1.0 8 nano100 series datasheet 0x400e_0000 C 0x400e_3fff adc12_ba 12 - bit analog - digital - converter (adc12) control registers apb2 modules space (0x4010_0000 ~ 0x401f_ffff) 0x4011_0000 C 0x4011_3fff tmr23_ba timer2 and timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 C 0x4013_3fff spi1_ba spi1 with master/slave function control registers 0x4014_0000 C 0x4014_3fff pwm1_ba pwm1 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x4019_0000 C 0x4019_3fff sc0_ba smartcard0 control registers 0x401a_0000 C 0x401a_3fff i2s_ba i 2 s control registers 0x401b_0000 C 0x401b_3fff sc1_ba smartcard1 control registers 0x401c_0000 C 0x401c_3fff sc2_ba smartcard2 control registers system control space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 C 0xe000_ecff scs_ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f scs_ba system control registers
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 103 of 160 revision 1.0 8 nano100 series datasheet 5.2 nested vectored interrupt controller (nvic) 5.2.1 overview the cortex - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic). it is closely coupled to the processor kernel and provides following features: 5.2.2 features ? nested and vectored interrupt support ? automatic processor state saving and restoration ? dynamic priority changing ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software . while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces dela y time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 104 of 160 revision 1.0 8 nano100 series datasheet 5.3 system manager 5.3.1 overview system manager mainly controls the power modes, wake - up source, system resets and system memory map. it also provides information about product id, chip reset, ip reset, and multi - function pin control. 5.3.2 features ? power modes and wake - up sources ? system resets ? system memory map ? system manager registers for : ? product id ? chip and ip reset ? multi - functional pin control
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 105 of 160 revision 1.0 8 nano100 series datasheet 5.4 clock controller 5.4.1 overview the clock controller generates clocks for the whole chip, i including system clocks (cpu clock, hclkx, and pclkx) and all peripheral engine clocks. hclkx means ahb bus clock for peripherals on ahb bus. pclkx means apb bus clock for peripherals on apb bus. t he clock controller also implements the power control function with the individually clock on/off control, clock source selection and a 4 - bit clock divider. the chip will not enter power - down mode until cpu sets the power down enable bit (pd_en) and cpu ex ecutes the wfi instruction. in the power - down mode, clock controller turns off the external high frequency crystal, internal high frequency oscillator, and system clocks (cpu clock, hclkx, and pclkx) to reduce the power consumption to minimum. 5.4.2 features ? ge nerates clocks for system clocks and all peripheral engine clocks. ? each peripheral engine clock can be turned on/off. ? high frequency crystal, internal high frequency oscillator, and system clocks will be turned off when chip is in power - down mode.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 106 of 160 revision 1.0 8 nano100 series datasheet 5.5 analog to digital converter (adc) 5.5.1 overview this chip contains one 12 - bit successive approximation analog - to - digital converter (sar a/d converter) with 12 external input channels and 6 internal channels. the a/d converter supports three operation modes: single, si ngle - cycle scan and continuous scan mode, and can be started by software and external stadc/pb.8 pin and timer event start. note that the i/o pins used as adc analog input pins must be configured as input type and off digital function (gpioa_offd) should be turned on before adc function is enabled. 5.5.2 features ? analog input voltage range: 0~vref (max to 3.6v) ? selectable 12 - bits, 10 - bits, 8 - bits and 6 - bits resolution ? supports sampling time settings (in adc_clk unit) for channel 0~11 individually and channel 12~ 17 share the same one sampling time setting ? supports two power - down modes: ? power - down mode ? standby mode ? up to 12 external analog input channels (channel0 ~ channel11), and 6 internal channels (channel12~channel17) converting six voltage sources, including dac0, dac1, internal band - gap voltage, internal temperature sensor output, avdd, and avss. ? maximum adc clock frequency is 42 mhz and each conversion is 19 clocks+ sampling time depending on the input resistance. ? three operating modes ? single mode: a/d con version is performed one time on a specified channel. ? single - cycle scan mode: a/d conversion is performed one cycle on all specified channels with the sequence from the lowest numbered channel to the highest numbered channel. ? continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion. ? an a/d conversion can be started by: ? software write 1 to adst bit ? external pin stadc ? selects one from four timer events (tmr0, tmr1, tmr 2 and tmr 3 ) that enable adc and transfer ad results by pdma ? conversion results held in data registers for each channel ? conversion result can be compared with a specified value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting. ? supports calibration and load calibration words capability.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 107 of 160 revision 1.0 8 nano100 series datasheet 5.6 digital to analog converter (dac) 5.6.1 overview dac is a 12 - bit voltage - output digital - to - analog converter. two dacs are implemented in this chip. 5.6.2 features dac is a 12 - bit voltage - out put dac. dac can use in conjunction with the pdma controller. when two dacs are present, they may be grouped together for synchronous update operation. features: ? int_vref or vref or avdd reference voltage selection ? synchronized update capability for two da cs ? dac maximum conversion rate is 500 ksps
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 108 of 160 revision 1.0 8 nano100 series datasheet 5.7 dma controller 5.7.1 overview the dma controller contains six channel peripheral direct memory access (pdma) controllers, a video direct memory access (vdma) controller and a cyclic redundancy check (crc) generator. the pdma controller can transfer data to and from memory or transfer data to and from apb devices. the dma has eight channels of dma including one channel vdma (memory - to - memory) and six channels pdma (peripheral - to - memory or memory - to - peripheral or memory - to - memory) and a crc controller. for channel0 vdma, it supports block transfer from memory to memory. for pdma channel (dma ch1~ch6), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. and for channel 0 vdma, there is a two - word buffer. software can stop the dma operation by disable pdma [pdmacen]/vdma [vdmacen]. software can recognize the completion of a dma operation by software polling or when it receives an internal dma interrupt. the dma controller can increase source or destination address, fixed or wrap around them as well. the dma controller also contains a cyclic redundancy check (crc) generator that can perform crc calculation with programmable polynomial settings. the crc engine support cpu pio mode and d ma transfer mode. 5.7.2 features seven dma channels and a crc generator: 1 vdma channel and 6 pdma channels. each channel can support a unidirectional transfer. amba ahb master/slave interface compatible, for data transfer and register read/write. hardware round robin priority scheme. ? vdma ? memory - to - memory transfer ? supports block transfer with stride ? supports word/half - word/byte boundary address ? supports address direction: increment and decrement ? pdma ? peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer ? supports word boundary address ? supports word alignment transfer length in memory - to - memory mode ? supports word/half - word/byte alignment transfer length in peripheral - to - memory and memory - to - peripheral mode ? supports word/half - word/b yte transfer data width from/to peripheral ? supports address direction: increment, fixed, and wrap around ? cyclic redundancy check (crc) ? supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 ? crc - ccitt: x 16 + x 12 + x 5 + 1 ? crc - 8: x 8 + x 2 + x + 1 ? crc - 16: x 16 + x 15 + x 2 + 1 ? crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 109 of 160 revision 1.0 8 nano100 series datasheet ? programmable seed value ? supports programmable order reverse setting for input data and crc checksum ? supports programmable 1s complement setting for input data and crc checksum ? supports cpu pio mode or dma transfer mode ? supports 8/16/32 - bit of data width in cpu pio mode ? 8 - bit write mode: 1 - ahb clock cycle operation ? 16 - bit write mode: 2 - ahb clock cycle operation ? 32 - bit write mode: 4 - ahb clock cycle operation ? supports byte alignment transfer length in crc dma mode
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 110 of 160 revision 1.0 8 nano100 series datasheet 5.8 external bus interface 5.8.1 overview this chip is equipped with an external bus interface (ebi) to access external device. to save the connections between external device and this chip, ebi support address bus and data bus multiplex mode. also, address latch enable (ale) signal is used to differentiate the address and data cycle. 5.8.2 features ? external devices with max. 64 kbytes size (8 - bit data width)/128 kbytes (16 - bit data width ) supported ? supports variable external bus base clock (mclk) ? supports 8 - bit or 16 - bit data width ? supports variable data access time (tacc), address latch enable time (tale) and address hold time (tahd) ? address bus and data bus multiplex mode supported to save the address pins ? configurable idle cycle supported for different access condition: write command finish (w2x), read - to - read (r2r), read - to - write (r2w) ? supports pdma and vdma transfer
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 111 of 160 revision 1.0 8 nano100 series datasheet 5.9 flash memory controller (fmc) 5.9.1 overview this chip is equipped with 32 k/64k/12 3 k bytes on - chip embedded flash eprom for application program memory (aprom) that can be updated through isp/iap procedure. in system programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip powered on cortex - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, this chip also provides data flash region, the data flash is shared with original program memory and its start address is configurable and defined by use r in config1. the data flash size is defined by user application request. 5.9.2 features ? ahb interface compatible ? run up to 42 mhz with zero wait state for discontinuous address read access ? 32/64/123kb application program memory (aprom) ? 4kb in system programmin g (isp) loader program memory (ldrom) ? programmable data flash start address and memory size with 512 bytes page erase unit ? in system program (isp)/in application program (iap) to update on chip flash eprom
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 112 of 160 revision 1.0 8 nano100 series datasheet 5.10 general purpose i/o controller 5.10.1 overview up to 86 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 86 pins are arranged in 6 ports named with gpioa, gpiob, gpioc, gpiod, gpioe and gpiof. ports a ~ e have the maximum of 16 pins while port f have 6 pins. each one of the 86 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be independently software configured as input, output, and open - drain mode. each i/o pin h as a very weak individual pull - up resistor which is about 110 k ? ~300 k ? for vdd from 1.8 v to 3.6 v. 5.10.2 features ? up to 86 general purpose i/o pins ? supports input, output, open - drain operation mode ? programmable de - bounce timing ? each i/o pin can be programmed as either edge - trigger or level - sensitive ? each i/o pin can be programmed as either low - level active or high - level active ? each i/o pin can be programmed as either falling - edge trigger or rising - edge trigger
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 113 of 160 revision 1.0 8 nano100 series datasheet 5.11 i 2 c 5.11.1 overview i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the b us simultaneously. serial, 8 - bit oriented bi - directional data transfers can be made up to 1.0 mbps. data is transferred between a master and a slave synchronously to scl on the sda line on a byte - by - byte basis. each data byte is 8 - bit long. there is one sc l clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. a transition on the sda line while scl is high is interpreted as a command (start or stop). each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. the controllers on - chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. th e i 2 c controller handles byte transfers autonomously. pull up resistor is needed for i 2 c operation as these are open drain pins. the i 2 c controller is equipped with two slave address registers. the contents of the registers are irrelevant when i 2 c is in ma ster mode. in the slave mode, the seven most significant bits must be loaded with the users own slave address. the i 2 c hardware will react if the contents of i2caddr are matched with the received slave address. this controller supports the general call ( gc) function. if the gc bit is set this controller will respond to general call address (00h). clear gc bit to disable general call function. when gc bit is set and the i 2 c is in slave mode, it can receive the general call address which is equal to 00h af ter master sends general call address to the i 2 c bus, then it will follow status of gc mode. if it is in master mode, the ack bit must be cleared when it sends general call address of 00h to the i 2 c bus. the i 2 c - bus controller supports multiple address rec ognition with two address mask register. when the bit in the address mask register is set to one, it means the received corresponding address bit is dont - care. if the bit is set to zero, that means the received corresponding register bit should be exact t he same as address register.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 114 of 160 revision 1.0 8 nano100 series datasheet 5.11.2 features ? acts as master or slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? one built - in 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable clock divider allows versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( two slave addresses with mask option) ? supports power - down wake - up function
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 115 of 160 revision 1.0 8 nano100 series datasheet 5.12 i 2 s 5.12.1 overview the audio controller consists of i 2 s protocol to interface with external audio codec. two 8 word deep fifo for receiving path and transmitting path respectively and is capable of handling 8 ~ 32 bit word si zes. pdma controller handles the data movement between fifo and memory. 5.12.2 features ? i 2 s can operate as either master or slave mode. ? capable of handling 8, 16, 24 and 32 bits word sizes. ? mono and stereo of audio data are supported. ? i 2 s and msb justified data format are supported. ? two fifo data buffers (each 32 bits) are provided, one is for transmitting and the other is for receiving. ? generate interrupt when buffer levels cross a programmable boundary. ? two pdma channels request, one is for transmitting and the other is for receiving.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 116 of 160 revision 1.0 8 nano100 series datasheet 5.13 lcd display driver 5.13.1 overview the lcd driver can directly drive a lcd glass by creating the ac segment and common voltage signals automatically. it can support static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty lcd glass with up to 38 segments with 6 com (segment 0 is used as lcd_com4 and segment 1 is used as lcd_com5) or 40 segments with 4 com (lcd_com0 ~ lcd_com3). a built - in charge pump function can be enabled to provide the lcd glass with higher voltage than the syste m voltage. the lcd driver would generate voltage higher than the threshold voltage in older to darken a segment and a voltage lower than threshold to make a segment clear. however, the lcd display segment will degrade if the applied voltage has a dc - compon ent. to avoid this, the generated waveform by lcd driver are arranged such that average voltage of each segment is zero and the rms(root - mean - square) voltage applied on a lcd segment lower than the segment threshold making lcd clear and rms voltage higher than the segment threshold making lcd dark. note : output voltage for adc/lcd shared pins cannot be high er than vdd because these pins are without 5v tolerance . (lqfp64 : lcd_seg17, lcd_seg19, lcd_seg20, lcd_seg21, lcd_seg22, lcd_seg23) (lqfp128 : lcd_seg36, lcd_seg37, lcd_seg38, lcd_seg39) 5.13.2 features ? supports up to 174 dots (6x 29 ) or 12 4 dots (4x3 1 ) in lqfp64 package and 228 dots (6x38) or 160 dots (4x40) in lqfp100/lqfp128 package segment/com pins: ? common 0 - 5 multiplexing functions with gpi/o pins ? segment 0 - 39 multiplexing function with gpi/o pins ? supports static,1/2 bias and 1/3 bias voltage ? six display modes: static,1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty or 1/6 duty selectable lcd frequency by frequency divider ? configurable frame frequency ? in ternal charge pump, adjustable contrast adjustment ? embedded lcd bias reference ladder (r - type, 200k ? resisters) ? configurable charge pump frequency ? blinking capability ? supports r/c - type method ? lcd frame interrupt
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 117 of 160 revision 1.0 8 nano100 series datasheet 5.14 pulse width modulation (pwm) 5.14.1 overview this c hip has two pwm controllers, each controller has 4 independent pwm outputs, ch0~ch3, or as 2 complementary pwm pairs, (ch0, ch1), (ch2, ch3) with 2 programmable dead - zone generators. each two pwm outputs, (ch0, ch1), (ch2, ch3), share the same 8 - bit presc aler, clock divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). each pwm output has independent 16 - bit pwm down - count counter for pwm period control, and 16 - bit comparators for pwm duty control. each dead - zone generator has two outputs. the f irst dead - zone generator output is ch0 and ch1, and for the second dead - zone generator, the output is ch2 and ch3. the 2 sets of pwm controller total provide eight independent pwm interrupt flags which are set by hardware when the corresponding pwm period down counter reaches zero. pwm interrupt will be asserted when both pwm interrupt source and its corresponding enable bit are active. each pwm output can be configured as one - shot mode to produce only one pwm cycle signal or continuous mode to output pwm w aveform continuously. when dzen01 of pwmx_ctl is set, ch0 and ch1 perform complementary pwm paired function; the paired pwm timing, period, duty and dead - time are determined by pwm channel 0 timer and dead - zone generator 0. similarly, when dzen23 of pwmx_c tl is set the complementary pwm pair of (ch2, ch3) is controlled by pwm channel 2. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to c ounter/comparator buffer registers the updated value will be loaded into the 16 - bit down counter/ comparator at the time down counter reaching zero. the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches zer o, the interrupt request is generated. if pwm output is set as continuous mode, when the down counter reaches zero, it is reloaded with cn of pwmx_dutyy(y=0~3) register automatically then start decreases, repeatedly. if the pwm output is set as one - shot mo de, the down counter will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse width modulation. the counter control logic changes the output level when down - counter value matches the value of compare register. the alternate feature of the pwm is digital input capture function. if capture function is enabled the pwm output pin is switched as capture input pin. the capture channel 0 and pwm ch0 share one timer; and the capture channel 1 and pwm ch1 share one timer, and etc. therefore user must setup the pwm timer before enabling capture feature. after capture feature is enabled, the capture always latches pwm timer to capture rising latch register (pwmx_crly) where y=0~3, when input channel has a rising transition and latches pwm timer to capture falling latch register (pwmx_cfly) where y=0~3, when input channel has a falling transition. capture channel 0 interrupt is programmable by setting pwmx_capinten. whenever capture event latched for channe l 0/1/2/3, the pwm timer 0/1/2/3 will be reload at this moment if the corresponding reload enable bit specified in capctl are set. the maximum captured frequency that pwm can capture is dominated by the capture interrupt latency. when capture interrupt occ urs, software will do at least three steps, they are: read pwmintsts to tell it from interrupt source and read pwmx_crly/pwmx_cfly(y=0~3) to get capture value and finally write 1 to clear pwmx_intsts. if interrupt latency will take time t0 to finish, the c apture signal mustnt transient during this interval . in this case, the maximum capture frequency will be 1/t0.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 118 of 160 revision 1.0 8 nano100 series datasheet 5.14.2 features 5.14.2.1 pwm function: ? two pwm controllers, each controller having 4 independent pwm outputs, ch0~ch3, or as 2 complementary pwm pairs, (ch0, ch1), (ch2, ch3) with 2 programmable dead - zone generators ? up to 8 pwm channels or 4 pwm paired channels ? up to 16 bits pwm counter width ? pwm interrupt request synchronous with pwm period ? single - shot or continuous mode ? four dead - zone generators 5.14.2.2 capture funct ion: ? timing control logic shared with pwm timer. ? 8 capture input channels shared with 8 pwm output channels. ? each channel supports one rising latch register (pwmx_crly), one falling latch register (pwmx_cfly) and capture interrupt flag (capify) where x=0~ 1,y=0~3. ? eight 16 - bit counters for eight capture channels or four 32 - bit counter for four capture channels when cascade is enabled: when ch01casken is set, the original 16 - bit counter of channel 1 will combine with channel 0s 16 bit counter for channel 0 input capture counting and so does ch23casken for channel 2, 3 ? supports pdma transfer function for pwmx channel 0, 2
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 119 of 160 revision 1.0 8 nano100 series datasheet 5.15 rtc 5.15.1 overview real time clock (rtc) unit provides user the real time and calendar message. the clock source of rtc is from an external 32.7 68 khz crystal connected at pins x32i and x32o (reference to pin description) or from an external 32.768 khz oscillator output fed at pin x32i. the rtc unit provides the time message (second, minute, hour) in time loading register (tlr) as well as calendar message (day, month, year) in calendar loading register (clr). the data message is expressed in bcd format. this unit offers alarm function that user can preset the alarm time in time alarm register (tar) and alarm calendar in calendar alarm register (car ). the rtc unit supports periodic time tick and alarm match interrupts. the periodic interrupt has 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0]). when rtc counter in tlr and clr is equal to alarm setting time registers tar and car, the alarm interrupt status (riir.ai s ) is set and the alarm interrupt is requested if the alarm interrupt is enabled (rier.aier=1). the rtc time tick (if wake - up cpu function is enabled, rtc_ttr[twke] high) and alarm matc h can cause cpu wake - up from idle or power - down mode. 5.15.2 features ? one time counter (second, minute, hour) and calendar counter (day, month, year) for user to check the time ? alarm register (second, minute, hour, day, month, year) ? 12 - hour or 24 - hour mode is sel ectable ? leap year compensation automatically ? day of week counter ? frequency compensate register (fcr) ? all time and calendar message is expressed in bcd code ? supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? supports rtc time tick and alarm match interrupt ? supports wake - up cpu from power - down mode ? supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers 5.16 smart card host interface (sc) 5.16.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standard and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. 5.16.2 features ? iso - 7816 - 3 t = 0, t = 1 compliant ? emv2000 compliant ? supports up to three iso - 7816 - 3 ports ? separates receive / transmit 4 byte entry buffer for data payloads ? programmable transmission clock frequency
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 120 of 160 revision 1.0 8 nano100 series datasheet ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? a 24 - bit and two 8 - bit counters for a nswer to reset (atr) and waiting times processing ? supports auto inverse convention function ? supports stop clock level and clock stop (clock keep) function ? supports transmitter and receiver error retry and error number limitation function ? supports hardware activation sequence process ? supports hardware warm reset sequence process ? supports hardware deactivation sequence process ? supports hardware auto deactivation sequence when detected the card removal. ? support uart mode ? half duplex, asynchronous communications ? separate receiving / transmitting 4 bytes entry fifo for data payloads ? support programmable baud rate generator for each channel ? support programmable receiver buffer trigger level ? programmable transmitting data delay ti me between the last stop bit leaving the tx - fifo and the de - assertion by setting scx_egtr [egt] register ? programmable even, odd or no parity bit generation and detection ? programmable stop bit, 1 or 2 stop bit generation
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 121 of 160 revision 1.0 8 nano100 series datasheet 5.17 spi 5.17.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol. devices communicate in master/slave mode with 4 - wire bi - direction interface. it is used to perform a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. the spi controller can be configured as a master or a slave devicee. the spi controller supports wake - up function. when this chip stays in power - down mode, it can be w aked up chip by off - chip device. this controller supports variable serial clock function for special application and 2 - bit transfer mode to connect 2 off - chip slave devices at the same time. the spi controller also supports pdma function to access the data buffer. 5.17.2 features ? supports master (max. 32 mhz) or slave (max. 16 mhz) mode operation ? supports 1 bit and 2 bit transfer mode ? support dual io transfer mode ? configurable bit length of a transaction from 8 to 32 - bit ? supports msb first or lsb first transfer sequence ? two slave select lines supported in master mode ? configurable byte or word suspend mode ? supports byte re - ordering function ? supports variable serial clock in master mode ? provide separate 8 - level depth transmit and receive fifo buffer ? supports wake - up function ? supports pdma transfer ? supports three wires, no slave select signal, bi - direction interface
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 122 of 160 revision 1.0 8 nano100 series datasheet 5.18 timer controller 5.18.1 overview this chip is equipped with four timer modules including timer0, timer1, timer2 and timer3 (timer0/1 is at apb1 and timer2/3 i s at apb2), which allow user to easily implement a counting scheme or timing control for applications. the timer can perform functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. the timer ca n generate an interrupt signal upon timeout, or provide the current value of count during operation. 5.18.2 features ? independent clock source for each timer (tmrx_clk, x= 0, 1,2,3) ? time - out period = (period of timer clock input) * (8 - bit pre - scale counter + 1) * (24 - bit tcmp) ? counting cycle time = (1 / tmrx_clk) * (2^8) * (2^24) ? internal 8 - bit pre - scale counter ? internal 24 - bit up counter is readable through tdr (timer data register) ? supports one - shot, periodic,output toggle and countinuous counting operation mode ? supports external pin capture for interval measurement ? supports external pin capture for timer counter reset ? supports inter - timer trigger ? supports internal trigger event to adc, dac and pdma
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 123 of 160 revision 1.0 8 nano100 series datasheet 5.19 uart controller 5.19.1 overview the uart controllers provides up to two channels of universal asynchronous receiver/transmitter (uart) modules that are uart0 and uart1. (uart0 is at apb1 and uart1 is at apb2). the universal asynchronous receiver/transmitter (uart) performs a serial - to - parallel conversion on data received fro m the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda (sir) function mode, lin master/slave function mode and rs - 485 function mode. each uart channel supports nine types of interrupts including receiver threshold level reaching interrupt (int_rda), transmitter fifo empty interrupt (int_thre), line status interrupt (break error, parity error, framing error or rs - 485 interrupt) (int_rls), time - out interrupt (int_tout), modem status inter rupt (int_modem), buffer error interrupt (int_buf_err), wake - up interrupt (int_wake), auto - baud rate detect or auto - baud rate counter overflow flag (int_abaud) and lin function interrupt (int_lin). the uart0 and uart1 are built - in with a 16 - byte transmitt er fifo (tx_fifo) and a 16 - byte receiver fifo (rx_fifo) that reduces the number of interrupts presented to the cpu. the cpu can read the status of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 3 error conditions (parity error, framing error or break interrupt) occur while receiving data. the uart controller supports auto - baud rate detection. the auto - baud rate detection controls th e process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user discretion. the uart controller also support incoming data or ctsn wake - up function. when the system is in power - down mode, an incoming dat a or ctsn signal will wake - up cpu from power - down mode. the uart includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / [brd + 1], where brd are defined in uart baud rate divider register (uartx_baud). below table lists the equations in the various conditions and the uart baud rate setting table. div_16_en brd baud rate equation disable (mode 0) a uart_clk / (a+1), a must >8 enable (mode 1) a uart_clk / [16 * (a+1)] table 5 ? 1 uart baud rate equation system clock =12 mhz baud rate mode 0 mode 1 921600 a=12 not supported 460800 a=25 not supported 230400 a=51 a=2 115200 a=103 a=6 57600 a=207 a=12 38400 a=311 a=19
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 124 of 160 revision 1.0 8 nano100 series datasheet 19200 a=624 a=38 9600 a=1249 a=77 4800 a=2499 a=155 table 5 ? 2 uart baud rate setting 5.19.1.1 auto - flow control the uart0 and uart1 controllers support auto - flow control function that uses two low - level signals, ctsn (clear - to - send) and rtsn (request - to - send) to control the flow of data transfer between the uart and external devices (ex: modem). when auto - flow is en abled, the uart is not allowed to receive data until the uart asserts rtsn (rtsn high) to external device. when the number of bytes in the rx - fifo equals the value of uart_tlctl [rts_tri_lev], the rtsn is de - asserted. the uart sends data out when uart cont roller detects ctsn is asserted (ctsn high) from external device. if a valid asserted ctsn is not detected the uart controller will not send data out. 5.19.1.2 auto - baud rate detection the uart0 and uart1 controllers support auto - baud rate detection. the auto - baud rate function can be used to measure the receiver incoming data baud rate. if enabled the auto - baud feature, uart controller will measure the bit time of the received data stream and set the divisor latch registers uart_bard. auto - baud rate detection is st arted by setting the uart_ctl [abaud_en]. 5.19.1.3 uart wake - up function the uart0 and uart1 controllers support wake - up system function. the wake - up function includes ctsn wake - up function (uart_ctl [wake_cts_en]) and data wake - up function (uart_ctl [wake_data_en]). when the system is operation in power - down mode, the uart can wake - up system by ctsn pin or by incoming data. 5.19.1.4 irda function mode the uart controllers also provi des serial irda (sir, serial infrared) function (user must set uart_fun_sel to select irda function). the sir specification defines a short - range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop bit. the maximum da ta rate is 115.2 kbps (half duplex). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half - duplex only. so it cannot transmit and receive data at the same time. the irda sir physical layer specifies a minimum 10 ms transfer delay between transmission and reception, and in irda operation mode the uart_baud setting must be mode1 (uart_baud [div_16_en] = 1). 5.19.1.5 rs - 485 function mode another alternate function of uart controllers is rs - 485 9 bit mode function whose direct ion control can be controlled by rtsn pin or gpio. the rs - 485 function mode is selected by setting the uart_fun_sel register to select rs - 485 function. the rs - 485 driver control is implemented by using the rtsn control signal from an asynchronous serial po rt to enable the rs - 485 driver. in rs - 485 mode, many characteristics of the rx and tx are same as uart. 5.19.1.6 lin function mode 5.19.2 the lin mode is selected by setting the lin_en bit in uart_fun_sel register. in lin mode, one start bit and 8 - bit data format with 1 - bit stop bit are required in accordance with the lin standard. features ? full duplex, asynchronous communications.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 125 of 160 revision 1.0 8 nano100 series datasheet ? separate receiving / transmitting 16 bytes entry fifo for data payloads. ? supports hardware auto - flow control/flow control function (ctsn, rtsn ) and programmable (ctsn, rtsn) flow control trigger level. ? supports programmable baud rate generator for each channel. ? supports auto - baud rate detect function. ? supports programmable receiver buffer trigger level. ? supports incoming data or ctsn to wake - up function. ? supports 9 bit receiver buffer time - out detection function. ? all uart channels can be served by the pdma controller. ? programmable transmitting data delay time between the last stop bit leaving the tx - fifo and the de - assertion by setting uart_tmctl [dly] register. ? supports break error, frame error, parity error and receiving / transmitting buffer overflow detect function. ? fully programmable serial - interface characteristics: ? programmable number of data bit, 5, 6, 7, 8 character. ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection. ? programmable stop bit, 1, 1.5, or 2 stop bit generation. ? supports irda sir function mode ? supports 3/16 bit period modulation. ? supports lin function mode. ? supports lin master/slave mode ? supports programmable break generation function for transmitter. ? supports break detect function for receiver. ? supports rs - 485 function mode. ? supports rs - 485 9bit mode. ? supports hardware or software controls rtsn or software control gpio to control transfe r direction.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 126 of 160 revision 1.0 8 nano100 series datasheet 5.20 usb 5.20.1 overview the usb controller is a usb 2.0 full - speed device controller. it is compliant with usb 2.0 full speed device specification and supports control/bulk/interrupt/isochronous transfer types. in this device controller, there are two ma in interfaces: the apb bus and usb bus which comes from the usb phy transceiver. for the apb bus, the cpu can program control registers through it. there is an internal 512 - byte sram as data buffer in this controller. for in token or out token transfer, it is necessary to write data to sram or read data from sram through the apb interface. users need to allocate the effective starting address of sram for each endpoint buffer through buffer segmentation register (bufseg). this device controller contains 8 configurable endpoints. each endpoint can be configured as in or out endpoint. the function address of the device and endpoint number in each endpoint shall be configured properly in advance for receiving or transmitting a data packet correctly. the transm itting/receiving length in each endpoint is defined in maximum payload register (mxpld) and the handshakes between host and device are also handled by it. there are four different interrupt events in this controller. they are the wake - up function, device p lug - in or plug - out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrupt, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowl edge what kind of events occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint. a software - disable function is also supported for this usb controller. it is used to simul ate the disconnection of this device from the host. if user enables the drvse0 bit (usb_ ctl[4] ), the usb controller will force usb_dp and usb_dm to level low and usb device function is disabled (disconnected). after disable the drvse0 bit, usb_dp will be p ulled high by internal pull - high circuit then host will enumerate the usb device connection again. reference: universal serial bus specification revision 2.0 5.20.2 features this universal serial bus (usb) performs a serial interface with a single connector type for attaching all usb peripherals to the host system. following is the feature listing of this usb. ? compliant with usb 2.0 full - speed specification. ? provide 1 interrupt vector with 4 different interrupt events (wakeup, fldet, usb and bus). ? supports control /bulk/interrupt/isochronous transfer type. ? supports suspend function when no bus activity existing for 3 ms. ? provide 8 endpoints for configurable control/bulk/interrupt/isochronous transfer types ? 512 - byte sram buffer inside ? provide remote wake - up capability.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 127 of 160 revision 1.0 8 nano100 series datasheet 5.21 watchdog timer controller 5.21.1 overview the purpose of watchdog timer is to perform a system reset after the software running into a problem. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up cpu from power - down mode. the watchdog timer includes an 18 - bit free running counter with programmable time - out intervals. 5.21.2 features ? 18 - bit free running wdt counter for watchdog timer time - out interval. ? selectable time - out interval (2^4 ~ 2^18) and the time - out interval is 104 ms ~ 26.316 s (if wdt_clk = 10 khz). ? reset period = (1 / 10 khz) * 63, if wdt_clk = 10 khz.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 1 28 of 160 revision 1.0 8 nano100 series datasheet 5.22 window watchdog timer controller 5.22.1 overview the purpose of window watchdog timer is to per form a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 5.22.2 features ? 6 - bit down counter and 6 - bit compare value to make the window period flexible ? selectable wwdt clock pre - scale cou nter to make wwdt time - out interval variable
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 129 of 160 revision 1.0 8 nano100 series datasheet 6 arm ? cortex? - m0 core 6.1 overview the cortex? - m0 processor is a configurable, multistage, 32 - bit risc processor. it has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex - m profile processor. the profile supports t w o modes C thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only b e issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. the following figure shows the functional controller of processor. figure 6 ? 1 m0 functional block 6.2 features ? a low gate count processor: ? armv6 - m thumb ? instruction set ? thumb - 2 technology ? armv6 - m compliant 24 - bit systick timer ? a 32 - bit hardware multiplier ? supports little - endian data accesses ? capable of deterministic, fixed - latency, interrupt handling ? load/store - multiples and multi - cycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling ? c application binary interface compliant exception model. this is the armv6 - m, c app lication binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers ? low power sleep mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or return from interrupt sleep - on - exit feature ? nvic: ? 32 external interrupt inputs, each with four levels of priority c o r t e x - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x - m 0 p r o c e s s o r c o r t e x - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 130 of 160 revision 1.0 8 nano100 series datasheet ? dedicated non - maskable interrupt (nmi) input ? supports for both level - sensitive and pulse - sensitive interrupt lines ? wake - up interrupt controller (wic), providing ultra - low power s leep mode support ? debug support: ? four hardware breakpoints ? two watch points ? program counter sampling register (pcsr) for non - intrusive code profiling ? single step and vector catch capabilities ? bus interfaces: ? single 32 - bit amba - 3 ahb - lite system interface p roviding simple integration to all system peripherals and memory ? single 32 - bit slave port that supports the dap (debug access port)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 131 of 160 revision 1.0 8 nano100 series datasheet 7 application circuit 7.1 lcd charge pump 7.1.1 c - type 1/3 bias 7.1.2 c - type 1/2 bias 7.1.3 internal r - type nano110/130 series mcus also support external r - type mode (bypass internal r) to reduce current consumption. for external r - type application, vlcd is normally connected to system vdd, or it can be connected to vdd through an external variable resistor (vr) which is used for adjusting lcd contrast. d h 1 v l c d 0 . 1 u f v 2 d h 2 v 1 v 3 n a n o 1 3 0 0 . 1 u f 0 . 1 u f 0 . 1 u f 0 . 1 u f d h 1 v l c d 0 . 1 u f v 2 d h 2 v 1 v 3 n a n o 1 3 0 0 . 1 u f 0 . 1 u f 0 . 1 u f 0 . 1 u f
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 132 of 160 revision 1.0 8 nano100 series datasheet 7.1.4 external r - type to reduce the current, the resistor ladder value can be increased. at some point, when the resistor ladder value is increased, the contrast will become affected and the waveform shape will be altered. therefore, capacitors around 0.1uf should be chosen and place closed to resistor ladder based on the contrast and size of the pixels on the glass. d h 1 v l c d v 2 d h 2 v 1 v 3 n a n o 1 1 0 n a n o 1 3 0 v d d v r 2 0 0 k 2 0 0 k 2 0 0 k d h 1 v l c d v 2 d h 2 v 1 v 3 n a n o 1 1 0 n a n o 1 3 0 v d d v r r 1 r 2 r 3
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 133 of 160 revision 1.0 8 nano100 series datasheet 7.2 adc application circuit 7.2.1 voltage reference source 7.2.1.1 avdd a v d d a v s s n a n o 1 0 0 a v d d v r e f a d c v r e f i n t v r e f a d 0 a d 1 a d 2 a d 3 a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 a d 1 0 a d 1 1 r e f s e l [ 1 : 0 ] o f a d c r a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e r e s e r v e r e f s e l [ 1 : 0 ] m u x e x t _ m o d e = 0 1 u f / / 0 . 1 f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f 0 0 0 1 1 0 1 1 d h 1 v l c d v 2 d h 2 v 1 v 3 n a n o 1 1 0 n a n o 1 3 0 v d d v r r 1 r 2 r 3 0 . 1 u f 0 . 1 u f 0 . 1 u f
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 134 of 160 revision 1.0 8 nano100 series datasheet 7.2.1.2 vref pin 7.2.1.3 int vref a v d d 1 u f / / 0 . 1 u f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f a v d d a v s s n a n o 1 0 0 a d 0 a d 1 a d 2 a d 3 a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 a d 1 0 a d 1 1 v r e f a d c v r e f i n t v r e f m u x e x t _ m o d e = 0 r e f s e l [ 1 : 0 ] r e f s e l [ 1 : 0 ] o f a d c r a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e r e s e r v e 0 0 0 1 1 0 1 1 a v d d 1 u f / / 0 . 1 u f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f a v d d a v s s v r e f a d 0 a d 1 a d 2 a d 3 a d 4 a d 5 a d 6 a d 7 a d 8 a d 9 a d 1 0 a d 1 1 n a n o 1 0 0 a d c v r e f i n t v r e f m u x e x t _ m o d e = 1 r e f s e l [ 1 : 0 ] r e f s e l [ 1 : 0 ] o f a d c r a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e r e s e r v e 0 0 0 1 1 0 1 1
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 135 of 160 revision 1.0 8 nano100 series datasheet 7.3 dac application circuit 7.3.1 voltage reference source 7.3.1.1 avdd 7.3.1.2 vref pin a v d d 1 u f / / 0 . 1 u f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f a v d d a v s s n a n o 1 0 0 v r e f d a c v r e f i n t v r e f d a c 1 _ o u t d a c 2 _ o u t r e f s e l [ 1 : 0 ] o f d a c a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e a v d d a s v o l t a g e r e f e r e n c e r e f s e l [ 1 : 0 ] m u x e x t _ m o d e = 0 0 0 0 1 1 0 1 1 a v d d 1 u f / / 0 . 1 u f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f a v d d a v s s n a n o 1 0 0 d a c 1 _ o u t d a c 2 _ o u t v r e f d a c v r e f i n t v r e f r e f s e l [ 1 : 0 ] m u x e x t _ m o d e = 0 r e f s e l [ 1 : 0 ] o f d a c a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e a v d d a s v o l t a g e r e f e r e n c e 0 0 0 1 1 0 1 1
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 136 of 160 revision 1.0 8 nano100 series datasheet 7.3.1.3 int vref a v d d 1 u f / / 0 . 1 u f v r e f i n c a s e v r e f = a v d d a v s s 1 u f / / 0 . 1 u f a v d d a v s s n a n o 1 0 0 d a c 1 _ o u t d a c 2 _ o u t v r e f d a c v r e f i n t v r e f r e f s e l [ 1 : 0 ] m u x e x t _ m o d e = 1 r e f s e l [ 1 : 0 ] o f d a c a v d d a s v o l t a g e r e f e r e n c e i n t . v r e f a s v o l t a g e r e f e r e n c e e x t . v r e f p i n a s v o l t a g e r e f e r e n c e a v d d a s v o l t a g e r e f e r e n c e 0 0 0 1 1 0 1 1
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 137 of 160 revision 1.0 8 nano100 series datasheet 7.4 whole chip application circuit pin27 pin102 pin100 pin103 pin104 pin105 pin101 pin28 pin107 pin108 pin124 pin58 pin63 pin62 pin59 pin61 pin64 c13 0.1uf c0603 u1 nano130_lqfp128 pb.9 64 pb.10 63 pb.11 62 nc 60 pe.6 58 pc.0 57 pc.1 56 pc.2 55 pc.3 54 pc.4 53 pc.5 52 pd.15 51 pd.14 50 pd.7 49 pd.6 48 pb.3 47 pb.2 46 pb.1 45 pb.0 44 usb_dp 43 usb_dm 42 vdd33 41 vbus 40 pe.7 38 pe.8 37 vss 29 nc 26 nc 23 pb.7 22 pb.6 21 pb.5 20 pb.4 19 pd.13 18 pd.12 17 pd.11 16 pd.10 15 pd.9 14 pd.8 13 pa.8 12 pa.9 11 pa.10 10 pa.11 9 x32i 7 x32o 6 pb.12 4 pb.13 3 pb.14 2 pe.13 1 pe.14 128 pe.15 127 pb.8 126 pvss 125 pf.5 123 pf.4 122 vdd 120 vss 117 reset 116 xt1_out 114 xt1_in 113 pb.15 111 pc.14 110 pc.15 109 pc.6 108 pc.7 107 pd.5 106 pd.4 105 pd.3 103 pd.2 102 pd.1 101 pd.0 100 nc 98 vref 97 pa.7 96 pa.6 95 pa.5 94 pa.4 93 pa.3 92 pa.2 91 pa.1 90 pa.0 89 avss 87 vss 85 nc 82 ice_ck/pf.1 81 ice_dat/pf.0 80 pa.12 79 pa.13 78 pa.14 77 pa.15 76 pc.8 75 pc.9 74 pc.10 73 pc.11 72 pc.12 71 pc.13 70 pe.0 69 pe.1 68 pe.2 67 pe.3 66 pe.4 65 vdd 83 vss 86 nc 84 avss 88 avdd 99 nc 112 nc 115 vss 118 nc 119 nc 121 vss 124 nc 5 nc 8 ldo 24 nc 25 vdd 27 nc 28 vss 30 vss 31 vss 32 pe.12 33 pe.11 34 pe.10 35 pe.9 36 nc 39 pe.5 61 vlcd 59 nc 104 pin121 tice_dat pin44 pin117 pin120 tice_rst tice_clk pin43 xtal1 pin118 pin40 pin119 pin42 pin39 pin35 pin38 tice_rst pin41 xtal2 pin114 pin33 pin37 xtal1 pin113 pin90 pin93 xtal2 pin86 pin83 pin87 pin91 pin8 pin82 pin89 pin9 pin1 pin4 pin7 x32ki pin2 pin85 pin92 pin84 pin5 pin3 pin6 x32ko pin24 pin21 pin20 pin18 pin15 pin17 pin16 pin14 pin13 pin12 pin11 pin10 pin22 pin19 pin54 pin47 pin56 pin55 pin45 pin50 pin53 pin46 pin52 pin49 pin48 pin57 pin51 pin96 tice_dat pin80 pin79 pin94 pin76 pin73 pin81 tice_clk pin74 pin95 pin77 pin72 pin78 pin75 pin88 pin36 pin125 pin106 pin112 pin128 pin126 pin110 pin111 pin109 pin115 r4 1m/dne 0603r c1 10uf/10v tant-a x2 12mhz xtal3-1 r2 33 0603r r1 10k 0603r jp4 header 5px2 header 5px2 1 2 3 4 5 6 7 8 9 10 c5 20pf 0603c c2 10uf/10v tant-a cb2 0.1uf c0603 cb3 0.1uf c0603 c3 20pf 0603c sw1 push button sw dvdd dvdd dvdd reset circuit ice interface from ice bridge's usb power dvdd c9 0.1uf c0603 cb5 0.1uf c0603 dvdd pin127 pin34 c12 1uf c0603 c14 1uf c0603 pin30 pin31 c10 1uf c0603 pin32 tice_rst pin116 dvdd pin69 pin65 pin66 pin71 pin67 pin68 pin70 dvdd pin123 c15 1uf c0603 pin98 pin23 pin60 x32ko x32ki c8 6pf 0603c c7 6pf 0603c crystal x1 32.768khz xtal3-1 dvdd pin97 pin99 cb4 0.1uf c0603 pin25 pin122 pin29 pin26
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 138 of 160 revision 1.0 8 nano100 series datasheet 8 power comsumption part no test condition vdd cpu clock current nano100 (b) series 128 kb flash 16 kb ram operating mode: cpu run while(1) in flash rom clock = 12 mhz crystal oscillator disable all peripherial 3.3v 12 m hz 2.41ma 200ua/mhz 1.8v 12 m hz n/a idle mode: cpu stop clock = 12 m hz crystal oscillator disable all peripherial 3.3v 12 m hz 900ua 75ua/mhz 1.8v 12 m hz n/a rtc + lcd mode: (ram retention) (power down with 32k and lcd enabled) cpu stop clock = 32.768 khz crystal oscillator disable all peripherial except rtc and lcd circuit without panel loading c - type 3.3v - 10ua internal r - type ( with 200k ) 8.5ua external r - type ( with 1m ) 4.5ua c - type/r - type 1.8v - n/a rtc mode: (ram retention) (power down with 32k enabled) cpu stop clock = 32.768 khz crystal oscillator disable all peripherial except rtc circuit 3.3v - 2.5ua 1.8v - 2.0ua power - down mode: (ram retention) cpu and all clocks stop 3.3v - 1ua 1.8v - 0.8ua wake - up from power - down mode 3.3v 7us n/a note: wake - up time: 7us from wake - up event to first cpu core valid clock; 10us from interrupt event to interrupt service routine first instruction.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 139 of 160 revision 1.0 8 nano100 series datasheet 9 electrical character istic 9.1 absolute max i mum ratings note : output voltage for adc/lcd shared pins cannot be high er than vdd because these pins are without 5v tolerance . (lqfp64 : lcd_seg17, lcd_seg19, lcd_seg20, lcd_seg21, lcd_seg22, lcd_seg23) (lqfp128 : lcd_seg36, lcd_seg37, lcd_seg38, lcd_seg39) 9.2 nano100/nano110/nano120/nano 130 dc electrical characteristics (vdd - vss=3.3v, ta = 25 ? c, fosc = 32 mhz unless otherwise specif ied.) parameter sym. specifications test conditions min. typ. max. unit operation voltage v dd 1.8 - 3.6 v v dd =1.8v up to 42 mhz power ground v ss av ss - 0.3 - v ldo output voltage v ldo1 1.62 1.8 1.98 v mcu operating in run or idle mode v ldo2 1.49 1.66 1.83 v mcu operating in power - down mode symbol parameter min max unit dc power supply v dd ? v ss - 0.3 +4.0 v input voltage on 5v tolerance pin v in v ss - 0.3 v dd +3.7 v input voltage on any other pin without 5v tolerance pin v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 +85 ? c storage temperature t st - 55 +150 ? c maximum current into vdd - 150 ma maximum current out of vss - 150 ma maximum current sunk by a i/o pin - 25 ma maximum current sourced by a i/o pin - 25 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 140 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test conditions min. typ. max. unit analog operating voltage av dd v dd v reference voltage vref 1.8 av dd v r un mode at irc = 12 mhz crystal oscillator disable all peripherial cpu run while(1) in flash rom clock = 12 mhz crystal oscillator disable all peripherial operating current run mode at xtal 12 mhz, hclk = 42 mhz i dd1 20.5 ma v dd = 3.6v at 42 mhz, all ip and pll enabled [*5] i dd2 10.6 ma v dd = 3.6v at 42 mhz all ip disabled and pll enabled i dd3 19.1 ma v dd = 1.8v at 42 mhz all ip and pll enabled [*5] i dd4 10.3 ma v dd = 1.8v at 42 mhz all ip disabled and pll enabled operating current run mode at xtal 12 mhz, hclk = 32 mhz i dd5 16.2 ma v dd = 3.6v at 32 mhz, all ip and pll enabled [*5] i dd6 8.3 ma v dd = 3.6v at 32 mhz all ip disabled and pll enabled i dd7 15.3 ma v dd = 1.8v at 32 mhz all ip and pll enabled [*5] i dd8 8.0 ma v dd = 1.8v at 32 mhz all ip disabled and pll enabled operating current run mode at xtal 12 mhz, hclk = 12 mhz i dd9 6.4 ma v dd = 3.6v at 12 mhz, all ip enabled and pll disabled i dd10 2.8 ma v dd = 3.6v at 12 mhz, all ip and pll disabled i dd11 6.3 ma v dd = 1.8v at 12 mhz, all ip enabled and pll disabled i dd12 2.8 ma v dd = 1.8v at 12 mhz, all ip and pll disabled operating current run mode i dd13 6.7 ma v dd = 3.6v at 12 m hz, all ip enabled and pll disabled
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 141 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test conditions min. typ. max. unit at irc 12 mhz, hclk = 12 mhz i dd14 3.0 ma v dd = 3.6v at 12 mhz, all ip and pll disabled i dd15 6.6 ma v dd = 1.8v at 12 mhz, all ip enabled and pll disabled i dd16 3.0 ma v dd = 1.8v at 12 mhz, all ip and pll disabled operating current run mode at xtal 4 mhz, hclk = 4 mhz i dd17 3.3 ma v dd = 3.6v at 4 mhz, all ip enabled and pll disabled i dd18 1.3 ma v dd = 3.6v at 4 mhz, all ip and pll disabled i dd19 3.2 ma v dd = 1.8v at 4 mhz, all ip enabled and pll disabled i dd20 1.3 ma v dd = 1.8v at 4 mhz, all ip and pll disabled operating current run mode at xtal 32.768 khz, hclk = 32.768 khz i dd21 82 ua v dd = 3.6v at 32.768 khz all ip enabled and pll disabled, i dd22 74 ua v dd = 3.6v at 32.768 khz all ip and pll disabled i dd23 77 ua v dd = 1.8v at 32.768 khz all ip enabled and pll disabled i dd24 68 ua v dd = 1.8v at 32.768 khz all ip and pll disabled operating current run mode at irc 10 khz, hclk = 10 khz i dd25 70 ua v dd = 3.6v at 10 khz all ip enabled and pll disabled i dd26 68 ua v dd = 3.6v at 10 khz all ip and pll disabled i dd27 65 ua v dd = 1.8v at 10 khz all ip enabled and pll disabled i dd28 62 ua v dd = 1.8v at 10 khz all ip and pll disabled operating current idle mode at xtal 12 mhz, hclk = 42 mhz i idle1 14.5 ma v dd = 3.6v at 42 mhz all ip and pll enabled [*5] i idle2 4.6 ma v dd =3.6v at 42 mhz all ip disabled and pll enabled
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 142 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test conditions min. typ. max. unit i idle3 13.8 ma v dd = 1.8v at 42mhz all ip and pll enabled [*5] i idle4 4.5 ma v dd = 1.8v at 42 mhz all ip disabled and pll enabled operating current idle mode at xtal 12 mhz, hclk = 32 mhz i idle5 11.6 ma v dd = 3.6v at 32 mhz all ip and pll enabled [*5] i idle6 3.6 ma v dd =3.6v at 32 mhz all ip disabled and pll enabled i idle7 11.1 ma v dd = 1.8v at 32mhz all ip and pll enabled [*5] i idle8 3.6 ma v dd = 1.8v at 32 mhz all ip disabled and pll enabled operating current idle mode at xtal 12 mhz, hclk = 12 mhz i idle9 4.7 ma v dd = 3.6v at 12 mhz, all ip enabled and pll disabled i idle10 0.99 ma v dd = 3.6v at 12 mhz, all ip and pll disabled i idle11 4.6 ma v dd = 1.8v at 12 mhz, all ip enabled and pll disabled i idle12 0.94 ma v dd = 1.8v at 12 mhz, all ip and pll disabled operating current idle mode at irc 12 mhz, hclk = 12 mhz i idle13 5.9 ma v dd = 3.6v at 12 mhz, all ip enabled and pll disabled i idle14 1.3 ma v dd = 3.6v at 12 mhz, all ip and pll disabled i idle15 4.9 ma v dd = 1.8v at 12 mhz, all ip enabled and pll disabled i idle16 1.3 ma v dd = 1.8v at 12 mhz, all ip and pll disabled operating current idle mode at xtal 4 mhz, hclk = 4 mhz i idle17 2.7 ma v dd = 3.6v at 4 mhz, all ip enabled and pll disabled i idle18 0.66 ma v dd = 3.6v at 4 mhz, all ip and pll disabled i idle19 2.7 ma v dd = 1.8v at 4 mhz, all ip enabled and pll disabled
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 143 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test conditions min. typ. max. unit i idle20 0.64 ma v dd = 1.8v at 4 mhz, all ip and pll disabled operating current idle mode at xtal 32.768 khz, hclk = 32.768 khz i idle21 78 ua v dd = 3.6v at 32.768 khz all ip enabled and pll disabled i idle22 69 ua v dd = 3.6v at 32.768 khz all ip and pll disabled i idle23 72 ua v dd = 1.8v at 32.768 khz all ip enabled and pll disabled i idle24 63 ua v dd = 1.8v at 32.768 khz all ip and pll disabled operating current idle mode at irc 10 khz, hclk = 10 khz i idle25 69 ua v dd = 3.6v at 10 khz all ip enabled and pll disabled i idle26 66 ua v dd = 3.6v at 10 khz all ip and pll disabled i idle27 63 ua v dd = 1.8v at 10 khz all ip enabled and pll disabled i idle28 61 ua v dd = 1.8v at 10 khz all ip and pll disabled standby current power - down mode i pwd1 1.2 ? a v dd = 3.6v, rtc off, all clock stop with ram retenstion, io no loading i pwd2 0.8 ? a v dd = 1.8v, rtc off, all clock stop with ram retenstion, io no loading i pwd3 2.8 ? a v dd = 3.6v, rtc on, all clock stop except 32.768 khz with ram retenstion, io no loading i pwd4 2.0 ? a v dd = 1.8v, rtc on, all clock stop except 32.768 khz with ram retenstion, io no loading input pull up resistor pa, pb, pc, pd, pe, pf r in 40 k v dd = 3.3v 98 k v dd = 1.8v input leakage current pa, pb, pc, pd, pe, pf i lk - 0.1 - +0.1 ? a v dd = 3.3v, 0 n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 144 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test conditions min. typ. max. unit input low voltage pa, pb, pc, pd, pe, pf (schmitt input) v il1 - 0.4v dd v input high voltage pa, pb, pc, pd, pe, pf (schmitt input) v ih1 0.6v dd 5.5 v adc and dac shared pins without input 5v tolerance. hysteresis voltage of pa~pf (schmitt input) v hy 0.2v dd v input low voltage xt1 _in / xt1_out [*2] v il2 0 - 0.4 v dd = 1 . 8 v input high voltage xt1 _in / xt1_out [*2] v ih2 1.5 - v dd +0.2 v v dd = 1 . 8 v input low voltage x32i / x32o [*2] v il4 0 - 0.3 v input high voltage x32 i / x32o [*2] v ih4 1.5 - 1.98 v negative going threshold (schmitt input), /reset v ils 1.28 1.33 1.37 v v dd = 3.3v positive going threshold (schmitt i put), /reset v ihs 1.75 1.98 2.25 v v dd = 3.3v source current pa, pb, pc, pd, pe, pf (push - pull mode) i sr21 - 10 - 14 - ma v dd = 3.3v, v s = vdd - 0.7v i sr22 - 3 - 5 - ma v dd = 1.8v, v s = vdd - 0.45v sink current pa, pb, pc, pd, pe, pf (push - pull mode) i sk21 10 15 - ma v dd = 3.3v, v s = 0.7v i sk22 3 6 - ma v dd = 1.8v, v s = 0.45v note: 1. /reset pin is a schmitt trigger input. 2. crystal input is a cmos input. 3. it is recommended that a 10uf or higher capacitor and a 100nf bypass capacitor are connected between vdd and the closest vss pin of the device. 4. for ensuring power stability, a 4.7uf or higher capacitor must be connected between ldo pin and the closest vss pin of the device. also a 100nf bypass capacitor between ldo and vss help suppressing output noise. 5. all peripherals clock source is from hxt ( 12 m hz), except spi from hclk.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 145 of 160 revision 1.0 8 nano100 series datasheet 9.3 ac electrical characteristics 9.3.1 external input clock parameter sym. specifications test condition min. typ. max. unit clock high time t chcx 10 - ns clock low time t clcx 10 - ns clock rise time t clch 2 - 15 ns clock fall time t chcl 2 - 15 ns note: duty cycle is 50%. 9.3.2 external 4~24 mhz xtal oscillator parameter sym. specifications test condition min. typ. max. unit oscillator frequency f hxt 4 12 24 mhz vdd = 1.8v ~ 3.6v temperature t hxt - 40 - +85 o c operating current i hxt 0.3 ma vdd = 3.0v 9.3.2.1 typical crystal application circuits crystal c1 c2 r 4mhz ~ 24 mhz optional(depend on crystal specification) without figure 9 ? 1 typical crystal application circuit t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d x t a l o u t x t a l i n c 1 c 2 r
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 146 of 160 revision 1.0 8 nano100 series datasheet 9.3.3 external 32.768 khz crystal parameter sym. specifications test condition min. typ. max. unit oscillator frequency f lxt 32.768 khz vdd = 1.8v ~ 3.6v temperature t lxt - 40 - +85 o c operating current i lxt 1.2 ? a vdd = 3.0v 9.3.4 internal 12 mhz oscillator parameter sym. specifications test condition min. typ. max. unit supply voltage [1] v hrc 1.8 v calibrated internal oscillator frequency f hrc 11.88 12 12.12 mhz 25 o c, v dd = 3v 11.76 12 12.24 mhz - 40 o c~+85 o c, v dd = 1.8v~3.6v 11.97 12 12.03 mhz - 40 o c~+85 o c, v dd = 1.8v~3.6v enable 32.768k crystal oscillator and set trim_sel[1:0]=10 operating current i hrc 450 ? a note: internal oscillator operation voltage comes from ldo. 9.3.5 internal 10 khz oscillator parameter sym. specifications test condition min. typ. max. unit supply voltage [1] v lrc 1.8 v center frequency f lrc 7 10 13 khz 25 o c, v dd = 3v 5 10 15 k ? hz - 40 o c~+85 o c, v dd = 1.8v~3.6v operating current i lrc 0.7 ? a v dd = 3v note: internal oscillator operation voltage comes from ldo. 9.4 analog characteristics 9.4.1 12 - bit adc parameter sym. specifications test condition min. typ. max. unit operating voltage av dd 1.8 3.6 v av dd = v dd
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 147 of 160 revision 1.0 8 nano100 series datasheet parameter sym. specifications test condition min. typ. max. unit operating current i adc 42 147 ? a av dd = v dd = 3.0v adc_vref = av dd adc clock rate = 42 mhz i adc 12 50 ? a av dd = v dd = 3.0v adc_vref = av dd adc clock rate = 12 mhz resolution r adc 12 bit reference voltage v ref 1.8 a v dd v reference input current (avg.) i ref 10 ? a adc input voltage v in 0 v ref v conversion time t conv 0.5 ? s sampling rate f sps 2m hz v dd = 3v integral non - linearity error inl 1 2 lsb v ref is external vref pin differential non - linearity dnl 0.8 - 1~+1.5 lsb v ref is external vref pin gain error e g - 2 lsb v ref is external vref pin offset error e offset - 3 lsb v ref is external vref pin absolute error e abs - 6 lsb v ref is external vref pin adc clock frequency f adc 0.25 42 mhz clock cycle ad cyc 20 cycle internal capacitance c in - 5 - pf monotonic - guaranteed - 9.4.2 brown - out detector parameter sym. specifications test condition min. typ. max. unit operating voltage v bod 1.8 3.6 v bod17 quiescent current i bod17 1 ? a av dd = 3.0v, bod17 enabled bod20 quiescent current i bod20 1 ? a av dd = 3.0v, bod20 enabled bod25 quiescent current i bod25 1 ? a av dd = 3.0v, bod25 enabled bod17 detection level v b17dt 1.6 1.7 1.8 v 25 ? c bod20 detection level v b20dt 1.9 2.0 2.1 v 25 o c bod25 detection level v b25dt 2.4 2.5 2.6 v 25 o c
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 148 of 160 revision 1.0 8 nano100 series datasheet 9.4.3 power - on reset parameter sym. specifications test condition min. typ. max. unit reset voltage v por - 1.6 - v quiescent current i por - 1 - na ldo output > reset voltage 9.4.4 temperature sensor parameter sym. specifications test condition (supply voltage = 3. 36v) min. typ. max. unit detection temperature t det - 40 + 110 o c operating current i temp - 5 - ? a gain v tg - 1. 80 - 1.73 - 1. 65 mv/ o c offset v to 73 0 740 750 mv tempeature at 0 o c note: internal operation voltage comes form ldo. 9.4.5 12 - bit dac parameter sym. specifications test condition min. typ. max. unit operating voltage av dd 2.0 3.6 v av dd = v dd operating current i dac 2.20 m a av dd = v dd = 3.0v , dac_vref = av dd d a c conversion rate 5 00khz resolution r adc 12 bit reference voltage v ref 1.8 a v dd v reference input current (avg.) i ref 0.85 m a av dd = v dd = 3.0v dac_vref=ext_vref d a c conversion rate 500khz dac output swin range v out 0.1 x v ref - 0.9 x v ref v conversion rate (code to adjacent code) f sps 5 00 khz v dd = 3v integral non - linearity error inl 4 5 lsb v ref is external vref pin not include offset and gain error differential non - linearity dnl 1 2 lsb v ref is external vref pin not include offset and gain error gain error e g 290 lsb offset error e offset 150 lsb
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 149 of 1 60 revision 1.0 8 nano100 series datasheet 9.4.6 lcd parameter sym. specifications test condition min. typ. max. unit operating voltage v dd 1.8 - 3.6 v vlcd voltage v lcd34 - 3.4 - v cpump_vol_set=111, no loading vlcd voltage v lcd33 - 3.3 - v cpump_vol_set=110, no loading vlcd voltage v lcd32 - 3.2 - v cpump_vol_set=101, no loading vlcd voltage v lcd31 - 3.1 - v cpump_vol_set=100, no loading vlcd voltage v lcd30 - 3.0 - v cpump_vol_set=011, no loading vlcd voltage v lcd29 - 2.9 - v cpump_vol_set=010, no loading vlcd voltage v lcd28 - 2.8 - v cpump_vol_set=001, no loading vlcd voltage v lcd27 - 2.7 - v cpump_vol_set=000, no loading operating current i lcd - 10 - ? a v dd = 3v, frame rate = 32hz without loading 9.4.7 internal voltage reference parameter sym. specifications test condition min. typ. max. unit operating voltage av dd 1.8 - 3.6 v 1.8v voltage reference v ref1 1.69 1.8 1.87 v av dd 2.0v ( - 40 ? c ~85 ? c ) 2.5v voltage reference v ref2 2.35 2.5 2.60 v av dd 2.8v ( - 40 ? c ~85 ? c ) stable time t reftab - 1 - ms operating current i vref - 30 - ? a av dd = 3v 9.4.8 usb phy specifications 9.4.8.1 usb phy dc electrical characteristics symbol parameter condition min. typ. max. unit v ih input high (driven) 2.0 - v v il input low - 0.8 v v di differential input sensitivity |padp - padm| 0.2 - v
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 150 of 160 revision 1.0 8 nano100 series datasheet v cm differential common - mode range includes v di range 0.8 - 2.5 v v se single - ended receiver threshold 0.8 - 2.0 v receiver hysteresis 200 mv v ol output low (driven) 0 - 0.3 v v oh output high (driven) 2.8 - 3.6 v v crs output signal cross voltage 1.3 - 2.0 v r pu pull - up resistor 1.425 - 1.575 k r pd pull - down resistor 14.25 - 15.75 k v trm termination voltage for upstream port pull up (rpu) 3.0 - 3.6 v z drv driver output resistance steady state drive* 10 c in transceiver capacitance pin to gnd - 20 pf *driver output resistance doesnt include series resistor resistance. 9.4.8.2 usb phy full - speed driver elevtrical characteristics symbol parameter condition min. typ. max. unit t fr rise time c l =50p 4 - 20 ns t ff fall time c l =50p 4 - 20 ns t frff rise and fall time matching t frff =t fr /t ff 90 - 111.11 % 9.4.8.3 usb phy power dissipation symbol parameter condition min. typ. max. unit i vddreg (full speed) vddd and vddreg supply current (steady state) standby 50 ua 9.4.8.4 usb ldo dc electrical characteristics symbol parameter condition min. typ. max. unit vbus 5 v v33 output voltage vbus = 5v, 25 ? c 2.97 3.3 3.63 v iop operation current 100 ua
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 151 of 160 revision 1.0 8 nano100 series datasheet 9.5 flash dc electrical characteristics symbol parameter min typ max unit test condition v fla [2] supply voltage 1.62 1.8 1.98 v n endur endurance 20000 cycles [1] t ret data retention 100 year t a = 2 5 t erase page erase time - 20 - ms t prog program time - 40 - us i dd1 read current 0.1 50 ma/mhz i dd2 program current 7 ma i dd3 erase current 7 ma notes: 1. number of program/erase cycles. 2. v fla is source from chip ldo output voltage. 3. guaranteed by design, not test in production.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 152 of 160 revision 1.0 8 nano100 series datasheet 10 package dimensions 10.1 lqfp 128 (14x14x1.4 mm footprint 2.0 mm)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 153 of 160 revision 1.0 8 nano100 series datasheet 10.2 lqfp 64 ( 10 x1 0 x1.4 mm footprint 2.0 mm)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 154 of 160 revision 1.0 8 nano100 series datasheet 10.3 lqfp 64 (7x7x1.4 mm footprint 2.0 mm)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 155 of 160 revision 1.0 8 nano100 series datasheet
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 156 of 160 revision 1.0 8 nano100 series datasheet 10.4 lqfp 48 (7x7x1.4 mm footprint 2.0 mm)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 157 of 160 revision 1.0 8 nano100 series datasheet 10.5 qfn48 (7x7x 0.85 mm)
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 158 of 160 revision 1.0 8 nano100 series datasheet 11 revision history date revision description 2012.10.11 1.00 initial release 2012.12.11 1.01 1. added smartcard uart mode description in pin description. 2. unified the abbreviation (tmr) in the timer controller section. 3. modified the specifications of external input clock. 4. added lcd com4 and com5 description for each pin description and diagram. 5. updated the adc enabled by timer event description in the adc section. 6. changed timer0/1 ch0/1 to timer x (x=0, 1, 2, 3) in the timer controller section. 2012.12.17 1.02 1. added description of reading ucid in isp mode. 2012.12.28 1.03 1. added r - type related description in lcd section. 2. updated the operating current data of run mode and idle mode at each frequency and added related data at 42 mhz in section 9.2. 2013.01.02 1.04 1. updated the table in power consumption section. 2013.0 3 . 05 1.0 5 1. updated the display modes from four to six in section 5.13.2 . 2. corrected the pin descriptions in section 3.4 . 3. updated temperature sensor of analog char a cteristic in section 9.4.4. 4. corrected smart card s feature to be half duplex in uart mode in section 5.16.2. 2013.0 5 .2 8 1.06 1. updated the nano110 lqfp128 - pin diagram in section 3.3.2 . 2. updated 12 mhz osc has 2 % deviation within all temperarure range in section s 2 .1 to 2.4 . 3. updated dac analog characteristic s in section 9.4.5. 4. added nano110rc2bn to the nano110 lcd line selection guide. 2013. 12 . 0 4 1.07 1. updated nano100 series selection code in section 3.1. 2. added the nano100 qfn48 package in section 3.2 and qfn48 package dimensions in chapter 10. 3. fixed the typo of lcd characteristic in section 9.4.7. 4. added a note that output voltage for adc/lcd shared pins cannot be higher than vdd because these pins are without 5v tolerance. for pin description in section 3.4, lcd overview in section 5.13.1 and absolute maximum ratings in section 9.1. 5. modified the schematic for adc and dac application circuit in section
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 159 of 160 revision 1.0 8 nano100 series datasheet 7. 2 and 7.3 . 2016.05 .31 1.08 1. added flash dc electrical characteristics in section 9.5 . 2. fixed the typo of lcd feature in section 5.13.2. 3. fixed the typo of products selection guide in section 3.2 4. modified the schematic for adc , dac and whole chip applicatio n c ircuit in section 7.2 , 7.3 and 7.4.
n u m icro ? nano100 (b) datasheet may 31 , 201 6 page 160 of 160 revision 1.0 8 nano100 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , insecure usage. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic s ignal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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